The geometric accuracy of topographic mapping with high-resolution remote sensing images is inevita-bly affected by the orbiter attitude jitter.Therefore,it is necessary to conduct preliminary research on the stereo m...The geometric accuracy of topographic mapping with high-resolution remote sensing images is inevita-bly affected by the orbiter attitude jitter.Therefore,it is necessary to conduct preliminary research on the stereo mapping camera equipped on lunar orbiter before launching.In this work,an imaging simulation method consid-ering the attitude jitter is presented.The impact analysis of different attitude jitter on terrain undulation is conduct-ed by simulating jitter at three attitude angles,respectively.The proposed simulation method is based on the rigor-ous sensor model,using the lunar digital elevation model(DEM)and orthoimage as reference data.The orbit and attitude of the lunar stereo mapping camera are simulated while considering the attitude jitter.Two-dimensional simulated stereo images are generated according to the position and attitude of the orbiter in a given orbit.Experi-mental analyses were conducted by the DEM with the simulated stereo image.The simulation imaging results demonstrate that the proposed method can ensure imaging efficiency without losing the accuracy of topographic mapping.The effect of attitude jitter on the stereo mapping accuracy of the simulated images was analyzed through a DEM comparison.展开更多
This paper focuses on anti-jamming and anti-eavesdropping problem in air-to-ground(A2G)communication networks considering the impact of body jitter of unmanned aerial vehicle(UAV).A full-duplex(FD)active ground eavesd...This paper focuses on anti-jamming and anti-eavesdropping problem in air-to-ground(A2G)communication networks considering the impact of body jitter of unmanned aerial vehicle(UAV).A full-duplex(FD)active ground eavesdropper launches jamming attack while eavesdropping to stimulate the legitimate transmitter(i.e.,UAV)to increase its transmission power.The legitimate transmitter’s objective is to against the simultaneous wiretapping and jamming with a robust and power-efficient transmission scheme.The active eavesdropper aims to minimize the system secrecy rate.To study the interaction between the legitimate transmitter and the active eavesdropper,a non-cooperative game framework is formulated.Detailed,considering the impact of UAV jitter on antenna array response and secrecy performance,we first investigate the UAV’s transmission power minimization problem for the worst scenario with minimum legitimate data rate and maximum eavesdropping data rate under UAV jitter.Then,the active eavesdropper’s secrecy rate minimization problem with the worst scenario is investigated by optimizing its jamming strategy.Nash equilibrium is proved to be existed and obtained with the proposed iterative algorithm.Finally,extensive numerical results are provided to evaluate the system secrecy performance and to show the secrecy performance gains of the proposed method.展开更多
A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and ...This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.展开更多
A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given....A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.展开更多
Passively mode-locked fiber lasers emit femtosecond pulse trains with excellent short-term stability. The quantum-limited timing jitter of a free running femtosecond erbium-doped fiber laser working at room temperatur...Passively mode-locked fiber lasers emit femtosecond pulse trains with excellent short-term stability. The quantum-limited timing jitter of a free running femtosecond erbium-doped fiber laser working at room temperature is considerably below one femtosecond at high Fourier frequency. The ultrashort pulse train with ultralow timing jitter enables absolute time-of-flight measurements based on a dual-comb implementation, which is typically composed of a pair of optical frequency combs generated by femtosecond lasers. Dead-zone-free absolute distance measurement with sub-micrometer precision and kHz update rate has been routinely achieved with a dual-comb configuration, which is promising for a number of precision manufacturing applications, from large step-structure measurements prevalent in microelectronic profilometry to three coordinate measurements in large-scale aerospace manufacturing and shipbuilding. In this paper, we first review the sub-femtosecond precision timing jitter characterization methods and approaches for ultralow timing jitter mode-locked fiber laser design. Then, we provide an overview of the state-of-the-art dual-comb absolute ranging technology in terms of working principles, experimental implementations, and measurement precisions. Finally, we discuss the impact of quantum-limited timing jitter on the dual-comb ranging precision at a high update rate. The route to highprecision dual-comb range finder design based on ultralow jitter femtosecond fiber lasers is proposed.展开更多
In this paper, the timing jitter in dispersion-managed soliton-like systems with the Caussian pulse is studied by using two methods. Firstly, the derivation of the dynamic equations for the evolution of soliton-like p...In this paper, the timing jitter in dispersion-managed soliton-like systems with the Caussian pulse is studied by using two methods. Firstly, the derivation of the dynamic equations for the evolution of soliton-like parameters and the timing jitter expressions for the dispersion-managed soliton-like systems are carried out by the perturbed variational method. By analysing and simulating these timing jitter expressions, one can find that the timing jitter is induced by the amplified spontaneous emission noise and the frequency shift, etc. Nonlinear gain can suppress the timing jitter. The chirp sign and the filters action have also effects on the total timing jitter. Secondly, the timing jitter is calculated and analysed by using the moment method. The results of the two methods prove to be consistent with each other.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
Network-induced delay and jitter are key factors causing performance degradation and instability of NCSs (networked control systems). The relationships between the sampling periods of the control loops, network-induce...Network-induced delay and jitter are key factors causing performance degradation and instability of NCSs (networked control systems). The relationships between the sampling periods of the control loops, network-induced delay and jitter were studied aimed at token-type networks. A jitter-dependent optimal bandwidth scheduling algorithm for NCSs is proposed, which tries to achieve a tradeoff between bandwidth occupancy and system performance. Simulation tests proved the effectiveness of this optimal scheduling algorithm.展开更多
A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of...A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.展开更多
基金Supported by the National Natural Science Foundation of China(42221002,42171432)Shanghai Municipal Science and Technology Major Project(2021SHZDZX0100)the Fundamental Research Funds for the Central Universities.
文摘The geometric accuracy of topographic mapping with high-resolution remote sensing images is inevita-bly affected by the orbiter attitude jitter.Therefore,it is necessary to conduct preliminary research on the stereo mapping camera equipped on lunar orbiter before launching.In this work,an imaging simulation method consid-ering the attitude jitter is presented.The impact analysis of different attitude jitter on terrain undulation is conduct-ed by simulating jitter at three attitude angles,respectively.The proposed simulation method is based on the rigor-ous sensor model,using the lunar digital elevation model(DEM)and orthoimage as reference data.The orbit and attitude of the lunar stereo mapping camera are simulated while considering the attitude jitter.Two-dimensional simulated stereo images are generated according to the position and attitude of the orbiter in a given orbit.Experi-mental analyses were conducted by the DEM with the simulated stereo image.The simulation imaging results demonstrate that the proposed method can ensure imaging efficiency without losing the accuracy of topographic mapping.The effect of attitude jitter on the stereo mapping accuracy of the simulated images was analyzed through a DEM comparison.
基金supported in part by the Beijing Municipal Natural Science Foundation under Grant 4212005in part by the National Natural Science Foundation of China under 62271076+1 种基金in part by Young Elite Scientists Sponsorship Program by CAST(YESS20200283)in part by the Fundamental Research Funds for the Central Universities under Grant 2242022k60006.
文摘This paper focuses on anti-jamming and anti-eavesdropping problem in air-to-ground(A2G)communication networks considering the impact of body jitter of unmanned aerial vehicle(UAV).A full-duplex(FD)active ground eavesdropper launches jamming attack while eavesdropping to stimulate the legitimate transmitter(i.e.,UAV)to increase its transmission power.The legitimate transmitter’s objective is to against the simultaneous wiretapping and jamming with a robust and power-efficient transmission scheme.The active eavesdropper aims to minimize the system secrecy rate.To study the interaction between the legitimate transmitter and the active eavesdropper,a non-cooperative game framework is formulated.Detailed,considering the impact of UAV jitter on antenna array response and secrecy performance,we first investigate the UAV’s transmission power minimization problem for the worst scenario with minimum legitimate data rate and maximum eavesdropping data rate under UAV jitter.Then,the active eavesdropper’s secrecy rate minimization problem with the worst scenario is investigated by optimizing its jamming strategy.Nash equilibrium is proved to be existed and obtained with the proposed iterative algorithm.Finally,extensive numerical results are provided to evaluate the system secrecy performance and to show the secrecy performance gains of the proposed method.
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
文摘This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.
文摘A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.
基金supported by National Natural Science Foundation of China (Grant Nos.61475162,61675150,and 61535009)Tianjin Natural Science Foundation (Grant No.18JCYBJC16900)Tianjin Research Program of Application Foundation and Advanced Technology (Grant No.17JCJQJC43500)
文摘Passively mode-locked fiber lasers emit femtosecond pulse trains with excellent short-term stability. The quantum-limited timing jitter of a free running femtosecond erbium-doped fiber laser working at room temperature is considerably below one femtosecond at high Fourier frequency. The ultrashort pulse train with ultralow timing jitter enables absolute time-of-flight measurements based on a dual-comb implementation, which is typically composed of a pair of optical frequency combs generated by femtosecond lasers. Dead-zone-free absolute distance measurement with sub-micrometer precision and kHz update rate has been routinely achieved with a dual-comb configuration, which is promising for a number of precision manufacturing applications, from large step-structure measurements prevalent in microelectronic profilometry to three coordinate measurements in large-scale aerospace manufacturing and shipbuilding. In this paper, we first review the sub-femtosecond precision timing jitter characterization methods and approaches for ultralow timing jitter mode-locked fiber laser design. Then, we provide an overview of the state-of-the-art dual-comb absolute ranging technology in terms of working principles, experimental implementations, and measurement precisions. Finally, we discuss the impact of quantum-limited timing jitter on the dual-comb ranging precision at a high update rate. The route to highprecision dual-comb range finder design based on ultralow jitter femtosecond fiber lasers is proposed.
文摘In this paper, the timing jitter in dispersion-managed soliton-like systems with the Caussian pulse is studied by using two methods. Firstly, the derivation of the dynamic equations for the evolution of soliton-like parameters and the timing jitter expressions for the dispersion-managed soliton-like systems are carried out by the perturbed variational method. By analysing and simulating these timing jitter expressions, one can find that the timing jitter is induced by the amplified spontaneous emission noise and the frequency shift, etc. Nonlinear gain can suppress the timing jitter. The chirp sign and the filters action have also effects on the total timing jitter. Secondly, the timing jitter is calculated and analysed by using the moment method. The results of the two methods prove to be consistent with each other.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
基金Project supported by the National Natural Science Foundation ofChina (Nos. 60074011 and 60174009), and Youth Science and Tech-nology Foundation of Shanxi Province (No. 20051020), China
文摘Network-induced delay and jitter are key factors causing performance degradation and instability of NCSs (networked control systems). The relationships between the sampling periods of the control loops, network-induced delay and jitter were studied aimed at token-type networks. A jitter-dependent optimal bandwidth scheduling algorithm for NCSs is proposed, which tries to achieve a tradeoff between bandwidth occupancy and system performance. Simulation tests proved the effectiveness of this optimal scheduling algorithm.
基金supported partly by National Natural Science Foundation of China(Nos.50637010,51077111)partly by the State Key Laboratory of Electrical Insulation and Power Equipment of Xi'an Jiaotong University of China(EIPE09207)
文摘A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.
