KEY OPTIMIZATION TECHNIQUES IN JPEG-LS IP CORE DESIGN

This paper presents the key optimization techniques for an efficient accelerator implementation in an image encoder IP core design for real-time Joint Photographic Experts Group Lossless(JPEG-LS) encoding.Pipeline architecture and accelerator elements have been utilized to enhance the throughput capability.Improved parameters mapping schemes and resource sharing have been adopted for the purpose of low complexity and small chip die area.Module-level and fine-grained gating measures have been used to achieve a low-power implementation.It has been proved that these hardware-oriented optimization techniques make the encoder meet the requirements of the IP core implementation.The proposed optimization techniques have been verified in the implementation of the JPEG-LS encoder IP,and then validated in a real wireless endoscope system.

A Novel Scheme for Compression of Cash Images

In the field of economy, there are more and more electronic scanning cash images, which need to be compressed in a higher compression ratio. This paper proposes a specific compression algorithm for cash images. First, according to cash image characteristics and standard JPEG （joint photographic experts group） compression, image re-ordering techniques are analyzed, and the method of modifying some blocks into single color blocks is adopted. Then, a suitable quantization table for cash images is obtained. Experimental results show that the method is effective.

Degradation algorithm of compressive sensing

The compressive sensing （CS） theory allows people to obtain signal in the frequency much lower than the requested one of sampling theorem. Because the theory is based on the assumption of that the location of sparse values is unknown, it has many constraints in practical applications. In fact, in many cases such as image processing, the location of sparse values is knowable, and CS can degrade to a linear process. In order to take full advantage of the visual information of images, this paper proposes the concept of dimensionality reduction transform matrix and then se- lects sparse values by constructing an accuracy control matrix, so on this basis, a degradation algorithm is designed that the signal can be obtained by the measurements as many as sparse values and reconstructed through a linear process. In comparison with similar methods, the degradation algorithm is effective in reducing the number of sensors and improving operational efficiency. The algorithm is also used to achieve the CS process with the same amount of data as joint photographic exports group （JPEG） compression and acquires the same display effect.

Social network structures among the livestock farmers vis a vis calcium supplement technology

This study aims to delineate and analyze the configuration of social networks of farmers with respect to the acquisition of information on vital livestock technology.Three stage sampling was carried out by interviewing 320 technology-adopter farmers from four districts of Kerala State in India.For mapping the network,social network analysis(SNA)was used,which revealed the important sources as well as patterns of information access by farmers.Results established the predominance of a formal communication source(veterinary doctor)in the study locales followed by small-sized peer groups of livestock farmers for crucial information support on technology use.The trend is observed irrespective of their gender in various study areas.Significantly the study thus,underscored the role of homogenous peer groups of farmers in facilitating meaningful interactions as well as information sharing on the technology.Given the low level of adoption of most livestock technologies along with the weak livestock extension machinery in the country,these findings could be used by extension agencies to strategize future technological interventions.

Design and verification of on-chip debug circuit based on JTAG

An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline control,hardware breakpoint/observation point,and parameter statistics.Compared with traditional debug mode,the proposed debug circuit completes direct transmission of data between peripherals and memory by adding data test-direct memory access(DT-DMA)module,which improves debug efficiency greatly.The proposed circuit was designed in a 0.18μm complementary metal-oxide-semiconductor(CMOS)process with an area of 167234.76μm~2 and a power consumption of 8.89 mW.And the proposed debug circuit and L-DSP were verified under a field programmable gate array(FPGA).Experimental results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than the CPU.