Synthesized Multi-station Tribo-test System for Bio-tribological Evaluation in Vitro

Tribological tests play an important role on the evaluation of long-term bio-tribological performances of prosthetic materials for commercial fabrication.Those tests focus on the motion simulation of a real joint in vitro with only normal loads and constant velocities,which are far from the real friction behavior of human joints characterized with variable loads and multiple directions.In order to accurately obtain the bio-tribological performances of artificial joint materials,a tribological tester with a miniature four-station tribological system is proposed with four distinctive features.Firstly,comparability and repeatability of a test are ensured by four equal stations of the tester.Secondly,cross-linked scratch between tribo-pairs of human joints can be simulated by using a gear-rack meshing mechanism to produce composite motions.With this mechanism,the friction tracks can be designed by varying reciprocating and rotating speeds.Thirdly,variable loading system is realized by using a ball-screw mechanism driven by a stepper motor,by which loads under different gaits during walking are simulated.Fourthly,dynamic friction force and normal load can be measured simultaneously.The verifications of the performances of the developed tester show that the variable frictional tracks can produce different wear debris compared with one-directional tracks,and the accuracy of loading and friction force is within ？5%.Thus the high consistency among different stations can be obtained.Practically,the proposed tester system could provide more comprehensive and accurate bio-tribological evaluations for prosthetic materials.

Investigation on the physical mechanism of cavity percentage dependent shear strength for rock joints considering the real contact joint surface

To explain the effect of joint roughness on joint peak shear strength(JPSS)and investigate the effect of different contact states of joint surface on JPSS,we try to clarify the physical mechanism of the effect of joint cavity percentage(JCP)on JPSS from the perspective of the three-dimensional(3D)distribution characteristics of the actual contact joint surface,and propose a JPSS model considering the JCP.Shear tests for red sandstone joints with three different surface morphologies and three different JCPs were performed under constant normal load condition.Based on test fitting results,the reduction effect of the JCP on JPSS is investigated,and a JPSS model for cavity-containing joints is obtained.However,the above model only considers the influence of JCP by fitting test data,and does not reveal the physical mechanism of JCP affecting the JPSS.Based on the peak dilation angle model for consideration of the actual contact joint morphology,and the influence of JCP on the roughness of the actual contact joint surface,a theoretical model of the JPSS considering the JCP is proposed.The derivation process does not depend on the test fitting,but is entirely based on the joint mechanical law,and its physical significance is clear.It is proposed that the essence of the influence of the JCP on JPSS is that the JCP first affects the normal stress of the actual contact joints,further affects the roughness of actual contact joints,and then affects the shear strength.

Design and verification of on-chip debug circuit based on JTAG

An on-chip debug circuit based on Joint Test Action Group(JTAG)interface for L-digital signal processor(L-DSP)is proposed,which has debug functions such as storage resource access,central processing unit(CPU)pipeline control,hardware breakpoint/observation point,and parameter statistics.Compared with traditional debug mode,the proposed debug circuit completes direct transmission of data between peripherals and memory by adding data test-direct memory access(DT-DMA)module,which improves debug efficiency greatly.The proposed circuit was designed in a 0.18μm complementary metal-oxide-semiconductor(CMOS)process with an area of 167234.76μm~2 and a power consumption of 8.89 mW.And the proposed debug circuit and L-DSP were verified under a field programmable gate array(FPGA).Experimental results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than the CPU.