Electric-field-dependent charge delocalization from dopant atoms in silicon junctionless nanowire transistor

We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping(below 30 K) and nearest-neighbor hopping(above 30 K).The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source–drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K.

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors （JNTs） are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures （10 K-100 K） and variable drain bias voltages （10 mV- 90 mV）. Transfer characteristics exhibit current oscillation peaks below flat-band voltage （VFB） at temperatures up to 75 K, which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional （1D） channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.

Observation of hopping transitions for delocalized electrons by temperature-dependent conductance in silicon junctionless nanowire transistors

We demonstrate transitions of hopping behaviors for delocalized electrons through the discrete dopant-induced quantum dots in n-doped silicon junctionless nanowire transistors by the temperature-dependent conductance characteristics.There are two obvious transition platforms within the critical temperature regimes for the experimental conductance data,which are extracted from the unified transfer characteristics for different temperatures at the gate voltage positions of the initial transconductance gm peak in Vg1 and valley in Vg2. The crossover temperatures of the electron hopping behaviors are analytically determined by the temperature-dependent conductance at the gate voltages Vg1 and Vg2. This finding provides essential evidence for the hopping electron behaviors under the influence of thermal activation and long-range Coulomb interaction.

Influence of dopant concentration on electrical quantum transport behaviors in junctionless nanowire transistors

We discuss the random dopant effects in long channel junctionless transistor associated with quantum confinement effects. The electrical measurement reveals the threshold voltage variability induced by the random dopant fluctuation. Quantum transport features in Hubbard systems are observed in heavily phosphorus-doped channel. We investigate the single electron transfer via donor-induced quantum dots in junctionless nanowire transistors with heavily phosphorus- doped channel, due to the formation of impurity Hubbard bands. While in the lightly doped devices, one-dimensional quantum transport is only observed at low temperature. In this sense, phonon-assisted resonant-tunneling is suppressed due to misaligned levels formed in a few isolated quantum dots at cryogenic temperature. We observe the Anderson-Mott transition from isolate electron state to impurity bands as the doping concentration is increased.

Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.

Electronic transport properties of silicon junctionless nanowire transistors fabricated by femtosecond laser direct writing

Silicon junctionless nanowire transistor（JNT） is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing（SS）,and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional（1D） subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm2·V-1·s-1,implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.

Transport spectroscopy through dopant atom array in silicon junctionless nanowire transistors

We demonstrate electron transport spectroscopy through a dopant atom array in n-doped silicon junctionless nanowire transistors within a temperature range from 6 K to 250 K. Several current steps are observed at the initial stage of the transfer curves below 75 K, which result from the electron transport from Hubbard bands to one-dimensional conduction band. The current-off voltages in the transfer curves have a strikingly positive shift below 20 K and a negative shift above 20 K due to the electrostatic screening induced by the ionized dopant atoms. There exists the minimum electron mobility at a critical temperature of 20 K, resulting from the interplay between thermal activation and impurity scattering. Furthermore, electron transport behaviors change from hopping conductance to thermal activation conductance at the temperature of 30 K.

Gate-regulated transition temperatures for electron hopping behaviours in silicon junctionless nanowire transistors

We investigate gate-regulated transition temperatures for electron hopping behaviours through discrete ionized dopant atoms in silicon junctionless nanowire transistors.We demonstrate that the localization length of the wave function in the spatial distribution is able to be manipulated by the gate electric field.The transition temperatures regulated as the function of the localization length and the density of states near the Fermi energy level allow us to understand the electron hopping behaviours under the influence of thermal activation energy and Coulomb interaction energy.This is useful for future quantum information processing by single dopant atoms in silicon.

Observation of source/drain bias-controlled quantum transport spectrum in junctionless silicon nanowire transistor

We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.

Coulomb blockade and hopping transport behaviors of donor-induced quantum dots in junctionless transistors

The ionized dopants, working as quantum dots in silicon nanowires, exhibit potential advantages for the development of atomic-scale transistors. We investigate single electron tunneling through a phosphorus dopant induced quantum dots array in heavily n-doped junctionless nanowire transistors. Several subpeaks splittings in current oscillations are clearly observed due to the coupling of the quantum dots at the temperature of 6 K. The transport behaviors change from resonance tunneling to hoping conduction with increased temperature. The charging energy of the phosphorus donors is approximately 12.8 meV. This work helps clear the basic mechanism of electron transport through donor-induced quantum dots and electron transport properties in the heavily doped nanowire through dopant engineering.

硅纳米线界面态的化学钝化方法概述

分析了界面态对硅无结纳米线晶体管（JNT）亚阈值摆幅和电导率的影响,并详细总结了化学钝化硅纳米线界面态的方法以及对器件性能的影响。化学钝化方法主要包括各向同性的氢氟酸（HF）腐蚀钝化和各向异性的四甲基氢氧化铵（TMAH）腐蚀钝化。HF钝化方法以氢饱和硅表面悬挂键来减少其表面界面态,TMAH钝化方法则通过各向异性腐蚀形成Si—O键。化学处理后得到了光滑的硅纳米线晶面表面结构,从而有效地抑制界面态对电导率的影响,使器件达到理想的亚阈值摆幅。研究结果表明,利用化学腐蚀钝化方法优化界面态,能够有效改善硅纳米线晶体管的性能。