Coulomb blockade and hopping transport behaviors of donor-induced quantum dots in junctionless transistors

The ionized dopants, working as quantum dots in silicon nanowires, exhibit potential advantages for the development of atomic-scale transistors. We investigate single electron tunneling through a phosphorus dopant induced quantum dots array in heavily n-doped junctionless nanowire transistors. Several subpeaks splittings in current oscillations are clearly observed due to the coupling of the quantum dots at the temperature of 6 K. The transport behaviors change from resonance tunneling to hoping conduction with increased temperature. The charging energy of the phosphorus donors is approximately 12.8 meV. This work helps clear the basic mechanism of electron transport through donor-induced quantum dots and electron transport properties in the heavily doped nanowire through dopant engineering.

Hetero-gate-dielectric double gate junctionless transistor(HGJLT)with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are： transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits （FOMs） are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate （L 1） for a given gate length （L） are also studied and the optimum lengths La under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.

Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor

We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor（DGJLT） for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.

Electric-field-dependent charge delocalization from dopant atoms in silicon junctionless nanowire transistor

We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping(below 30 K) and nearest-neighbor hopping(above 30 K).The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source–drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K.

Influence of dopant concentration on electrical quantum transport behaviors in junctionless nanowire transistors

We discuss the random dopant effects in long channel junctionless transistor associated with quantum confinement effects. The electrical measurement reveals the threshold voltage variability induced by the random dopant fluctuation. Quantum transport features in Hubbard systems are observed in heavily phosphorus-doped channel. We investigate the single electron transfer via donor-induced quantum dots in junctionless nanowire transistors with heavily phosphorus- doped channel, due to the formation of impurity Hubbard bands. While in the lightly doped devices, one-dimensional quantum transport is only observed at low temperature. In this sense, phonon-assisted resonant-tunneling is suppressed due to misaligned levels formed in a few isolated quantum dots at cryogenic temperature. We observe the Anderson-Mott transition from isolate electron state to impurity bands as the doping concentration is increased.

Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm^2·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–Si O2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.

Electronic transport properties of silicon junctionless nanowire transistors fabricated by femtosecond laser direct writing

Silicon junctionless nanowire transistor（JNT） is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing（SS）,and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional（1D） subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm2·V-1·s-1,implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors （JNTs） are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures （10 K-100 K） and variable drain bias voltages （10 mV- 90 mV）. Transfer characteristics exhibit current oscillation peaks below flat-band voltage （VFB） at temperatures up to 75 K, which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional （1D） channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.

Observation of hopping transitions for delocalized electrons by temperature-dependent conductance in silicon junctionless nanowire transistors

We demonstrate transitions of hopping behaviors for delocalized electrons through the discrete dopant-induced quantum dots in n-doped silicon junctionless nanowire transistors by the temperature-dependent conductance characteristics.There are two obvious transition platforms within the critical temperature regimes for the experimental conductance data,which are extracted from the unified transfer characteristics for different temperatures at the gate voltage positions of the initial transconductance gm peak in Vg1 and valley in Vg2. The crossover temperatures of the electron hopping behaviors are analytically determined by the temperature-dependent conductance at the gate voltages Vg1 and Vg2. This finding provides essential evidence for the hopping electron behaviors under the influence of thermal activation and long-range Coulomb interaction.

Transport spectroscopy through dopant atom array in silicon junctionless nanowire transistors

We demonstrate electron transport spectroscopy through a dopant atom array in n-doped silicon junctionless nanowire transistors within a temperature range from 6 K to 250 K. Several current steps are observed at the initial stage of the transfer curves below 75 K, which result from the electron transport from Hubbard bands to one-dimensional conduction band. The current-off voltages in the transfer curves have a strikingly positive shift below 20 K and a negative shift above 20 K due to the electrostatic screening induced by the ionized dopant atoms. There exists the minimum electron mobility at a critical temperature of 20 K, resulting from the interplay between thermal activation and impurity scattering. Furthermore, electron transport behaviors change from hopping conductance to thermal activation conductance at the temperature of 30 K.

Gate-regulated transition temperatures for electron hopping behaviours in silicon junctionless nanowire transistors

We investigate gate-regulated transition temperatures for electron hopping behaviours through discrete ionized dopant atoms in silicon junctionless nanowire transistors.We demonstrate that the localization length of the wave function in the spatial distribution is able to be manipulated by the gate electric field.The transition temperatures regulated as the function of the localization length and the density of states near the Fermi energy level allow us to understand the electron hopping behaviours under the influence of thermal activation energy and Coulomb interaction energy.This is useful for future quantum information processing by single dopant atoms in silicon.

Observation of source/drain bias-controlled quantum transport spectrum in junctionless silicon nanowire transistor

We investigate the influence of source and drain bias voltages(V_(DS))on the quantum sub-band transport spectrum in the 10-nm width N-typed junctionless nanowire transistor at the low temperature of 6 K.We demonstrate that the transverse electric field introduced from V_(DS) has a minor influence on the threshold voltage of the device.The transverse electric field plays the role of amplifying the gate restriction effect of the channel.The one-dimensional(1D)-band dominated transport is demonstrated to be modulated by V_(DS) in the saturation region and the linear region,with the sub-band energy levels in the channel(E_(channel))intersecting with Fermi levels of the source(E_(fS))and the drain(E_(fD))in turn as V_(g) increases.The turning points from the linear region to the saturation region shift to higher gate voltages with V_(DS) increase because the higher Fermi energy levels of the channel required to meet the situation of E_(fD)=E_(channel).We also find that the bias electric field has the effect to accelerate the thermally activated electrons in the channel,equivalent to the effect of thermal temperature on the increase of electron energy.Our work provides a detailed description of the bias-modulated quantum electronic properties,which will give a more comprehensive understanding of transport behavior in nanoscale devices.

A laterally graded junctionless transistor

This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.

Lateral-Coupled Junctionless IZO-Based Electric-Double-Layer Thin-Film Transistors Gated by Solid-State Phosphorosilicate Glass Electrolyte

We describe the lateral-coupled junctionless indium-zinc-oxide （IZO） thin-film transistors （TFTs） in which there are no junctions between channel and source/drain electrodes and with solid-state phosphorosilieate glass electrolyte （PSG） gating. Due to the three-dimensional high proton conduction and lateral coupled electric-double- layer （EDL） capacitance （〉 1 #Flora2） of the PSG, the low voltage （2.0 V） junctionless IZO TFTs and the dual eoplanar gate devices are obtained. An AND logic function is demonstrated on the basis of the junctionless EDL-TFTs. Such devices are promising for applications in pH sensors, humidity sensors, biosensors, and neuron network simulation.

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.

全环绕栅极场效应晶体管的Ⅰ-Ⅴ模型紧凑建模

基于表面电势提出了一种无结型全环绕栅极场效应晶体管的Ⅰ-Ⅴ模型。以一维泊松方程为基础,结合相应的边界条件,采用四阶龙格库塔算法对两个解析模型中基于物理原理的非线性超越方程组依次求解,建立了表面电势、中点电势与栅极电压相关的数值模型。随后,根据数值模型中以中间参数形式表示的表面电势结果,利用Pao-Sah积分推导出全环绕栅极场效应晶体管的漏极电流。所提出的Ⅰ-Ⅴ模型结果与数值和实验数据均显示出良好的一致性,验证了该建模方法用于全环绕栅极场效应晶体管的可行性。此外,该方法实现了解析模型与数值模型的结合,在精度和效率之间实现了很好的平衡。

不同温度下JLNT-FET和IMNT-FET的模拟/射频特性

无结纳米管场效应晶体管(JLNT-FET)和反转模式纳米管场效应晶体管(IMNT-FET)因具有较好的驱动能力和对短沟道效应(SCE)卓越的抑制能力被广泛研究。基于Sentaurus TCAD数值模拟,分析了环境温度对JLNT-FET和IMNT-FET的模拟/射频(RF)特性的影响,对比研究了JLNT-FET和IMNT-FET由于掺杂浓度和传导方式不同导致的性能差异。结果表明,随着温度升高,载流子声子散射加剧,器件的寄生电容增加,导致器件的模拟/RF性能下降。体传导的JLNT-FET受到声子散射影响较小,所以其漏源电流受温度影响比表面传导的IMNT-FET小。另外,JLNT-FET的载流子迁移率受沟道重掺杂影响,导致其驱动能力和模拟/RF性能都比IMNT-FET差。研究结果对进一步优化这两类器件及其在电路中的应用具有一定的参考意义。

The effect of random dopant fluctuation on threshold voltage and drain current variation in junctionless nanotransistors

We investigate the effect of dopant random fluctuation on threshold voltage and drain current variation in a two-gate nanoscale transistor. We used a quantum-corrected technology computer aided design simulation to run the simulation （10000 randomizations）. With this simulation, we could study the effects of varying the dimensions （length and width）, and thicknesses of oxide and dopant factors of a transistor on the threshold voltage and drain current in subthreshold region （off） and overthreshold （on）. It was found that in the subthreshold region the variability of the drain current and threshold voltage is relatively fixed while in the overthreshold region the variability of the threshold voltage and drain current decreases remarkably, despite the slight reduction of gate voltage diffusion （compared with that of the subthreshold）. These results have been interpreted by using previously reported models for threshold current variability, load displacement, and simple analytical calculations. Scaling analysis shows that the variability of the characteristics of this semiconductor increases as the effects of the short channel increases. Therefore, with a slight increase of length and a reduction of width, oxide thickness, and dopant factor, we could correct the effect of the short channel.