Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Trap-assisted tunneling（TAT） has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor（TFET）. In this paper, we assess subthreshold performance of double gate TFET（DG-TFET） through a band-to-band tunneling（BTBT） model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile（D_（it）） and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current.

Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer

A new T-shaped tunnel field-effect transistor(TTFET) with gate dielectric spacer(GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling(BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap(GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling （BTBT） efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane＇s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.

Double-gate-all-around tunnel field-effect transistor

In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.

Comparison of tunneling currents in graphene nanoribbon tunnel field effect transistors calculated using Dirac-like equation and Schrodinger’s equation

The tunneling current in a graphene nanoribbon tunnel field effect transistor(GNR-TFET) has been quantum mechanically modeled. The tunneling current in the GNR-TFET was compared based on calculations of the Dirac-like equation and Schrodinger’s equation. To calculate the electron transmittance, a numerical approach-namely the transfer matrix method(TMM)-was employed and the Launder formula was used to compute the tunneling current. The results suggest that the tunneling currents that were calculated using both equations have similar characteristics for the same parameters, even though they have different values. The tunneling currents that were calculated by applying the Dirac-like equation were lower than those calculated using Schrodinger’s equation.

Si–Ge based vertical tunnel field-effect transistor of junction-less structure with improved sensitivity using dielectric modulation for biosensing applications

A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.

A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors

Nanowires with gate-all-around(GAA) structures are widely considered as the most promising candidate for 3-nm technology with the best ability of suppressing the short channel effects,and tunneling field effect transistors(TFETs)based on GAA structures also present improved performance.In this paper,a non-quasi-static(NQS) device model is developed for nanowire GAA TFETs.The model can predict the transient current and capacitance varying with operation frequency,which is beyond the ability of the quasi-static(QS) model published before.Excellent agreements between the model results and numerical simulations are obtained.Moreover,the NQS model is derived from the published QS model including the current-voltage(I-V) and capacitance-voltage(C-V) characteristics.Therefore,the NQS model is compatible with the QS model for giving comprehensive understanding of GAA TFETs and would be helpful for further study of TFET circuits based on nanowire GAA structure.

Design and Analysis of Graphene Based Tunnel Field Effect Transistor with Various Ambipolar Reducing Techniques

The fundamental advantages of carbon-based graphene material,such as its high tunnelling probability,symmetric band structure(linear dependence of the energy band on the wave direction),low effective mass,and characteristics of its 2D atomic layers,are the main focus of this research work.The impact of channel thickness,gate under-lap,asymmetric source/drain doping method,workfunction of gate contact,and High-K material on Graphene-based Tunnel Field Effect Transistor(TFET)is analyzed with 20 nm technology.Physical modelling and electrical characteristic performance have been simulated using the Atlas device simulator of SILVACO TCAD with user-defined material syntax for the newly included graphene material in comparison to silicon carbide(SiC).The simulation results in significant suppression of ambipolar current to voltage characteristics of TFET and modelled device exhibits a significant improvement in subthreshold swing(0.0159 V/decade),the ratio of Ion/Ioff(1000),and threshold voltage(-0.2 V with highly doped p-type source and 0.2 V with highly doped n-type drain)with power supply of 0.5 V,which make it useful for low power digital applications.

Tunneling field effect transistors based on in-plane and vertical layered phosphorus heterostructures

Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here,we investigate the TFETs based on two different integration types： in-plane and vertical heterostructures composed of two kinds of layered phosphorous（β-P and δ-P） by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio（PVR）when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of - 10-6 and a steeper subthreshold swing（SS） of - 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of theβ-P and δ-P layers in the in-plane and vertical heterostructures.

Characteristics of cylindrical surrounding-gate GaAs_xSb_(1-x)/In_yGa_(1-y)As heterojunction tunneling field-effect transistors

A Ⅲ-Ⅴ heterojunction tunneling field-effect transistor(TFET) can enhance the on-state current effectively,and GaAsSb/InGaAs heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition.In this paper,the performance of the cylindrical surrounding-gate GaAsSb/InGaAs heterojunction TFET with gate-drain underlap is investigated by numerical simulation.We validate that reducing drain doping concentration and increasing gate-drain underlap could be effective ways to reduce the off-state current and subthreshold swing(SS),while increasing source doping concentration and adjusting the composition of GaAsSbInGaAs can improve the on-state current.In addition,the resonant TFET based on GaAsSb/InGaAs is also studied,and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current,respectively,and is much superior to the conventional TFET.

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor （LTFET） with a symmetric heteromaterial gate is proposed. Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.

Ge/Si heterojunction L-shape tunnel field-effect transistors with hetero-gate-dielectric

A Ge/Si heterojunction L-shaped tunnel field-effect transistor combined with hetero-gate-dielectric （GHL-TFET） is proposed and investigated by TCAD simulation. Current-voltage characteristics, energy-band diagrams, and the distri- bution of the band-to-band tunneling （BTBT） generation rate of GHL-TFET are analyzed. In addition, the effect of the vertical channel width on the ON-current is studied and the thickness of the gate dielectric is optimized for better suppression of ambipolar current. Moreover, analog/RF figure-of-merits of GHL-TFET are also investigated in terms of the cut-off frequency and gain bandwidth production. Simulation results indicate that the ON-current of GHL-TFET is increased by about three orders of magnitude compared with that of the conventional L-shaped TFET. Besides, the introduction of the hetero-gate-dielectric not only suppresses the ambipolar current effectively but also improves the analog/RF performance drastically. It is demonstrated that the maximum cut-off frequency of GHL-TFET is about 160 GHz, which is 20 times higher than that of the conventional L-shaped TFET.

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.

High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply

We present a GaSb/In As junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology.Numerical simulations resulted in an IOFF of 8×10^-17A/ m, ION of 9 A/ m, ION/IOFF of 1×10^11,subthreshold slope of 9.33 m V/dec and DIBL of 87 m V/V for GaSb/InAs JLTFET at a temperature of 300 K,gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.

Design and investigation of dopingless double-gate line tunneling transistor: Analog performance, linearity, and harmonic distortion analysis

The tunnel field-effect transistor (TFET) is proposed by using the advantages of dopingless and line-tunneling technology. The line tunneling is created due to the fact that the gate electric field is aligned with the tunneling direction, which dramatically enhances tunneling area and tunneling current. Moreover, the effects of the structure parameters such as the length between top gate and source electrode, the length between top gate and drain electrode, the distance between bottom gate and drain electrode, and the metal position on the on-state current, electric field and energy band are investigated and optimized. In addition, analog/radio-frequency performance and linearity characteristics are studied. All results demonstrate that the proposed device not only enhances the on/of current ratio and reduces the subthreshold swing, but also offers eight times improvement in cut-off frequency and gain band product as compared with the conventional point tunneling dopingless TFET, at the same time;it shows better linearity and small distortions. This proposed device greatly enhances the potential of applications in dopingless TFET.

Quantum confinement effects and source-to-drain tunneling in ultra-scaled double-gate silicon n-MOSFETs

By using the linear combination of bulk band （LCBB） method incorporated with the top of the barrier splitting （TBS） model, we present a comprehensive study on the quantum confinement effects and the source-to-drain tunneling in the ultra-scaled double-gate （DG） metal-oxide semiconductor field-effect transistors （MOSFETs）. A critical body thickness value of 5 nm is found, below which severe valley splittings among different X valleys for the occupied charge density and the current contributions occur in ultra-thin silicon body structures. It is also found that the tunneling current could be nearly 100% with an ultra-scaled channel length. Different from the previous simulation results, it is found that the source-to-drain tunneling could be effectively suppressed in the ultra-thin body thickness （2.0 nm and below） by the quantum confinement and the tunneling could be suppressed down to below 5% when the channel length approaches 16 nm regardless of the body thickness.

Analog performance of double gate junctionless tunnel field effect transistor

For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.

P-type double gate junctionless tunnel field effect transistor

We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material （TiO2） of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high IoN of ～ 0.3 mA/μm, a low/OFF of ～ 30 fA/μm, a high ION/IOFF ratio of ～ 1×10^10, a subthreshold slope （SS） point of ～ 23 mV/decade, and an average SS of ～ 49 mV/decade at a supply voltage of -1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.

Dynamic threshold voltage operation in Si and SiGe source junctionless tunnel field effect transistor

We propose a dynamic threshold voltage j unctionless tunnel FET （DT-JLTFET） in wnlcn me mresnolu voltage can be dynamically adjusted, resulting in higher ON-current. Through 2D numerical simulations, it is presented that the threshold voltage in the DT-JLTFET can be adjusted by applying a voltage to the adjust gate. The impact of the threshold voltage shift on the overall performance of the device is also studied. A comparison is made between the dynamic threshold voltage characteristics of a silicon JLTFET and a Sio.7Geo.3 source JLTFET.

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.