Flip Chip技术在集成电路封装中的应用

阐述从集成电路封装发展现状、Flip Chip技术内涵、Flip Chip技术在集成电路封装中的应用剖析、市场发展展望等多个角度,探讨在集成电路封装中,应用Flip Chip技术的必要性和重要性。

Drop failure modes of Sn-3.0Ag-0.5Cu solder joints in wafer level chip scale package

To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.

Integrated power electronics module based on chip scale packaged power devices

High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.

A transceiver frequency conversion module based on 3D micropackaging technology

The idea of Ku-band transceiver frequency conversion module design based on 3D micropackaging technology is proposed. By using the double frequency conversion technology,the dual transceiver circuit from Ku-band to L-band is realized by combining with the local oscillator and the power control circuit to complete functions such as amplification, filtering and gain. In order to achieve the performance optimization and a high level of integration of the Ku-band monolithic microwave integrated circuits(MMIC) operating chip, the 3 D vertical interconnection micro-assembly technology is used. By stacking solder balls on the printed circuit board(PCB), the technology decreases the volume of the original transceiver to a miniaturized module. The module has a good electromagnetic compatibility through special structure designs. This module has the characteristics of miniaturization, low power consumption and high density, which is suitable for popularization in practical application.

Integrated physics package of a chip-scale atomic clock

The physics package of a chip-scale atomic clock （CSAC） has been successfully realized by integrating vertical cavity surface emitting laser （VCSEL）, neutral density （ND） filter, λ/4 wave plate, 87Rb vapor cell, photodiode （PD）, and magnetic coil into a cuboid metal package with a volume of about 2.8 cm3. In this physics package, the critical component, 87Rb vapor cell, is batch-fabricated based on MEMS technology and in-situ chemical reaction method. Pt heater and thermistors are integrated in the physics package. A PTFE pillar is used to support the optical elements in the physics package, in order to reduce the power dissipation. The optical absorption spectrum of 87Rb D1 line and the microwave frequency correction signal are successfully observed while connecting the package with the servo circuit system. Using the above mentioned packaging solution, a CSAC with short-term frequency stability of about 7 × 10^-10τ-1/2 has been successfully achieved, which demonstrates that this physics package would become one promising solution for the CSAC.

Thermal-Mechanical Simulation and Analysis on Structural Caused Package Induced Stress in Stacked Chip Scale Package

Stacked chip scale package(SCSP) attracts more and more attentions in advanced packages application with light weight,thin and small size,high reliability,low power and high storage capability.However,more and more physical and electrical issues being caused by package-induced stress in SCSP were reported recently.The effect of structural factors,including die thickness,die attach film thickness,die attach film type,and spacer size on package induced stress,was investigated.Analyses were given based on simulation results and provide important suggestion for package design.

The Numerical Analysis of Strain Behavior at Solder Joint and Interface of Flip Chip Package

The flip chip package is a kind of advanced electri ca l packages. Due to the requirement of miniaturization, lower weight, higher dens ity and higher performance in the advanced electric package, it is expected that flip chip package will soon be a mainstream technology. The silicon chip is dir ectly connected to printing circuit substrate by SnPb solder joints. Also, the u nderfill, a composite of polymer and silica particles, is filled in the gap betw een the chip and substrate around the solder joints to improve the reliabili ty of solder joints. When flip chip package specimen is tested with thermal cycl ing, the cyclic stress/strain response that exists at the underfill interfaces and solder joints may result in interfacial crack initiation and propagation. Therefore, the chip cracking and the interfacial delamination between underfill and chip corner have been investigated in many studies. Also, most researches h ave focused on the effect of fatigue and creep properties of solder joint induce d by the plastic strain alternation and accumulation. The nuderfill must have lo w viscosity in the liquid state and good adhesion to the interface after solidif ying. Also, the mechanical behavior of such epoxy material has much dependen ce on temperature in its glass transition temperature range that is usually cove red by the temperature range of thermal cycling test. Therefore, the materia l behavior of underfill exists a significant non-linearity and the assumption o f linear elastic can lack for accuracy in numerical analysis. Through numerical analysis, this study had some comparisons about the effect of linear and non -linear properties of underfill on strain behaviors around the interface of fli p chip assembly. Especially, the deformation tendency inside solder bumps could be predicted. Also, it is worthily mentioned that we have pointed out which comp onent of plastic strain, thus, either normal or shear, has dominant influence to the fatigue and creep of solder bump, which have not brought up before. About the numerical analysis to the thermal plastic strain occurs in flip chip i nterconnection during thermal cycling test, a commercial finite element software , namely, ANSYS, was employed to simulate the thermal cycling test obeyed by MIL-STD-883C. The temperatures of thermal cycling ranged from -55 ℃ to 125 ℃ with ramp rate of 36 ℃/min and a dwell time of 25 min at peak temperature. T he schematic drawing of diagonal cross-section of flip chip package composed of FR-4 substrate, silicon chip, underfill and solder bump was shown as Fig.1. Th e numerical model was two-dimensional (2-D) with plane strain assumption and o nly one half of the cross-section was modeled due to geometry symmetry. The dim ensions and boundary conditions of numerical model were shown in Fig.2. The symm etric boundary conditions were applied along the left edge of the model, and the left bottom corner was additional constrained in vertical direction to prevent body motion. The finite element meshes of overall and local numerical model was shown as Fig.3. In this study, two cases of material model were used to describe the material behavior of the underfill: the case1 was linear elastic model that assumed Young’s Modulus (E) and thermal expansion coefficient (CTE) were consta nt during thermal cycling; the case2 was MKIN model (in ANSYS) that had nonlinea r temperature-dependent stress-strain relationship and temperature-dependent CTE. The material model applied to the solder bump was ANAND model (in ANSYS) th at described time-dependent plasticity phenomenon of viscoplastic material. Bot h the FR-4 substrate and silicon chip were assumed as temperature-independent elastic material; moreover, FR-4 substrate is orthotropic while silicon chip is isotropic. From the comparison between numerical results of linear and nonlinear material a ssumption of underfill, (i.e. case1 and case2), the quantities of plastic strain around the interconnection from case1 are higher than that in case2. Thus, the linear

人工智能芯片先进封装技术

随着人工智能(AI)和集成电路的飞速发展,人工智能芯片逐渐成为全球科技竞争的焦点。在后摩尔时代,AI芯片的算力提升和功耗降低越来越依靠具有硅通孔、微凸点、异构集成、Chiplet等技术特点的先进封装技术。从AI芯片的分类与特点出发,对国内外典型先进封装技术进行分类与总结,在此基础上,对先进封装结构可靠性以及封装散热等方面面临的挑战进行总结并提出相应解决措施。面向AI应用,对先进封装技术的未来发展进行展望。

倒装焊芯片封装微通孔的一种失效机理及其优化方法

随着晶圆工艺节点的发展,封装集成度越来越高,封装有机基板的线宽和线距逐步减少,微通孔的数量增加,微通孔的孔径减少。球栅阵列(BGA)封装有机基板的微通孔失效一直是影响高性能和高密度芯片封装可靠性的主要问题。针对有机基板微通孔失效的问题,通过温度循环可靠性试验、有限元分析方法、聚焦离子束、扫描电子显微镜以及能谱仪等表征手段,系统研究了-65℃~150℃与-55℃~125℃500次温度循环加载条件下倒装焊的失效模式。结果表明,在-65℃~150℃温度循环条件下,有机基板微通孔由温度循环疲劳应力而产生微通孔分层,仿真表明-65℃~150℃下基板平均等效应力增加约8 MPa;通过改善散热盖结构,等效应力降低了21.4%,且能通过-65℃~150℃500次温度循环的可靠性验证,满足高可靠性的要求。

Ka频段卫通收发共口径多波束相控阵封装天线设计

为满足卫星通信中双频共口径、高集成、多波束等要求,提出了一种基于封装天线(Antenna in Package, AIP)架构的Ka频段收发共口径多波束相控阵天线。天线以双频堆叠微带单元的形式实现了收发共口径,并通过天线集成滤波器保证了收发通道的隔离度优于44 dB。在±60°范围内,64元接收阵增益优于17.4 dB,128元发射阵增益优于20.2 dB,具有良好的波束扫描性能。为获得收发多波束一片式集成,在收发(Transmitter/Receiver, T/R)组件中使用晶圆级三维系统集成封装(Three Dimensions System in Package, 3D-SIP)并结合微凸点的制备技术,保证了系统级芯片(System-on-Chip, SOC)的高密度二次集成。高低频混压技术同样被应用于阵面、收发网络、控制供电链路的多层板集成。所提多波束的相控阵天线新架构具有高密度集成TR组件、多波束一体化、高效散热等特点,在卫星通信和数据链等方面具有广阔的应用前景。

采用大芯片的高功率密度SiC功率模块设计

碳化硅SiC(silicon carbide)器件具备耐高压、低损耗和高热导率等优势,对电动汽车行业发展具有重要意义。提出一种利用大芯片封装的SiC MOSFET功率模块设计,并开展实验分析模块的电气性能;搭建仿真对仅有电特性与电特性和温度负反馈结合这2种情况下模块温度进行对比研究。仿真结果表明,在相同工作条件下,采用大芯片封装设计的SiC MOSFET功率模块导通电流能力更强,温度变化更小,电气性能有所提升。

基于机器视觉的芯片缺陷检测研究进展

半导体芯片作为集成电路的重要组成部分,对其质量要求越来越高,因芯片在小型化、高密度的制造过程中产生缺陷,进而影响了芯片的性能和寿命。因此,缺陷的检测与识别对芯片可靠性的提升十分重要。综述了近10年来国内外基于机器视觉的芯片缺陷检测方法的研究进展。首先介绍了芯片的制造流程以及当前主流的芯片封装技术。然后概述了用于芯片缺陷成像的主流无损检测技术,主要包括光学成像、声学成像、红外热成像、电磁成像与X射线成像等技术。接着分别重点阐述了基于传统技术和基于深度学习的芯片表面的缺陷检测方法。随后按照缺陷部位比较分析了芯片封装体的缺陷检测方法。最后总结芯片缺陷检测当前存在的问题,对未来的研究方向进行了展望。

具有片上电感的改进型梯形声表面波滤波器

针对小体积声表面波(SAW)滤波器性能受封装影响较大的问题,提出了一种新型SAW梯形滤波器电路拓扑结构。通过分析滤波器高频受封装影响造成的远端抑制上翘的现象,从电路结构出发,改变版图设计,实现了片上电感。采用传统梯形滤波器结构和利用纵向耦合双模谐振器型滤波器(DMS)特殊接地结构相结合的电路拓扑结构,有助于提高带外抑制和设计灵活性。在标准的42°Y-X钽酸锂(LiTaO_(3))基板上制作滤波器,通过仿真分析得到中心频率2580 MHz、带宽50 MHz、插入损耗小于2.5 dB的高阶梯形射频SAW滤波器的最优拓扑结构。测试结果表明,通过改变电路拓扑结构关键参数和引入新的传输零点,可改善在高频段内的带外抑制特性。

压阻式压力传感器芯片悬空型无引线封装结构的设计与实验

传感器的无引线封装技术取消了传统的引线键合连接,因而在极端环境下,具有耐高温、抗冲击能力强等特点,有广阔的发展前景。但在常规无引线封装结构中,芯片与玻璃基座烧结固连,会受到高温热固耦合下的热应力影响,进而降低测量精度。针对这一问题,以压阻式压力传感器芯片作为封装对象,提出了一种芯片悬空型无引线封装结构,对其封装材料的选择进行了研究并对整体热应力分布及大小进行了仿真分析;通过实验探究了封装结构中金属电极-导电银浆-金属插针电学互连通道在高温环境下的电学稳定性和力学强度;对采用该封装结构的压力传感器样品进行了输出和温度性能测试。结果表明,该封装结构整体所受热应力显著低于常规结构;电学互连通道的接触电阻远小于芯片压敏电阻,高低温循环条件下其阻值变化小于14Ω;高低温冲击后其拉伸破坏拉力在1.2 N以上;传感器样品输出电压线性度良好,在25~225℃内最大热零点漂移小于0.01%FS/℃,最大热满量程输出漂移小于0.20%FS/℃,相比于常规无引线封装结构显著减小了传感器热零点漂移,验证了该封装结构的可行性,为解决常规无引线封装结构中芯片热应力自释放问题提供了一个新的研究思路。

集成DTC的埋入硅桥式扇出型封装的去耦设计

对于供电网络面临的电源完整性挑战,采用一种集成深槽电容(DTC)的埋入硅桥式扇出型封装结构,以改善其供电性能。介绍了硅桥芯片和DTC的制作工艺以及DTC与埋入硅桥芯片的连接方式,并对硅桥芯片、DTC分别进行仿真,以验证DTC的去耦效果。进一步研究了集成DTC的埋入硅桥式扇出型封装、在基板背贴硅电容的扇出型封装和无去耦电容的扇出型封装3种方案对电源分配网络(PDN)阻抗的去耦效果。通过对比3种方案的仿真结果,发现埋入硅桥式扇出型封装结构的自阻抗值和转移阻抗值较在基板背贴硅电容的扇出型封装结构分别低74%和95%,较无去耦电容的扇出型封装结构分别低91%和97%。

基于倒装焊的大尺寸芯片塑封工艺研究

基于倒装焊的大尺寸芯片塑封工艺,研究了4000 pin级电路封装工艺试验,对大尺寸芯片倒装、回流焊接、底填以及4000 pin级植球等关键工艺步骤进行了研究和评估。工艺试验结果表明工艺能力可以较好地覆盖4000 pin级倒装芯片球栅格阵列(FCBGA)电路塑料封装。可靠性测试结果表明,4000 pin级FCBGA塑料封装电路高温贮存(150℃)可达1000 h,温循寿命(-65℃~150℃)可达500次,强加速稳态湿热试验(130℃/85%)可达96 h,且环境试验后的电路通断测试正常。

基于叠层组装和双腔体结构的高密度集成技术

针对高功能密度集成的需求及系统级封装的关键技术,重点介绍了双腔体的结构设计思路、三维芯片堆叠技术、引脚成型技术,并进行了难点分析。通过客户使用工艺性设计模拟分析的结果显示:芯片、元器件超过200℃的时间均控制在25 s以内,双腔体封装后的产品经过回流焊接,温度分布对元器件影响不大,产品元件的可耐受峰值温度和时间可控。通过可靠性模拟分析,温度循环条件下,芯片和低应力粘接胶、陶瓷片材料参数存在差异,芯片内部会产生内应力,叠层芯片受到的最大等效应力100 MPa,温度变化对系统级封装中三维堆叠芯片的可靠性评估非常重要。基于真实的产品数据进行温度冲击、随机振动、恒定加速度模拟分析,结果证明选择的低应力粘接胶和双腔体结构设计能够满足产品高可靠的需求。

高压大功率IGBT器件绝缘结构的电场计算研究综述

随着高压直流输电技术的发展,高压大功率绝缘栅双极型晶体管(insulated gate bipolar transistor,IGBT)器件被广泛应用于各类高压大容量电力换流和控制装备中。然而,在高压大功率IGBT器件的研制过程以及工程应用中,器件内部局部放电现象乃至击穿现象频繁发生,给器件绝缘设计带来巨大挑战。要想实现良好器件绝缘设计,就需要获得器件内部的电场分布,因此实现器件内部电场的准确计算至关重要。文中全面回顾器件内部绝缘结构的建模和计算方法的发展历程,从封装绝缘电场计算、芯片绝缘电场计算以及芯片和封装绝缘耦合电场计算3个方面介绍相关研究的发展历程、适用范围以及相应的不足,最后展望未来器件内绝缘结构电场计算的发展方向。

一种基于倒装芯片的超宽带BGA封装差分传输结构

随着高速数字电路和射频微波电路对时钟频率和带宽的要求越来越高,差分传输结构因其优良的噪声抑制和抗干扰性能而受到越来越多的重视。提出了一种基于倒装芯片的超宽带球栅阵列(BGA)封装差分传输结构。整体传输结构包括采用陶瓷材料制作的倒装芯片用基板、BGA封装焊球和印制电路板(PCB)。主要分析了差分垂直传输结构的尺寸参数对阻抗和截止频率的影响,并利用阶梯过孔减小阻抗不连续性。整体结构的传输性能通过矢量网络分析仪测试的散射参数来表征。测试与仿真结果具有较好的一致性,在DC~60 GHz频段,差分传输结构的回波损耗≤-15 dB,插入损耗优于-1 dB,为超宽带倒装芯片的封装设计提供参考。