针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,...针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。展开更多
With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Curren...With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.展开更多
Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,eas...Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.展开更多
A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET lo...A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.展开更多
A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a...A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0. 9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply.展开更多
A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled ...A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.展开更多
Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor netwo...Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.展开更多
The current research of nuclear control rod drive mechanism(CRDM)movable latch only makes a simple measurement of wear mass.The wear volume and difference in various claw surfaces are ignored and the degradation mecha...The current research of nuclear control rod drive mechanism(CRDM)movable latch only makes a simple measurement of wear mass.The wear volume and difference in various claw surfaces are ignored and the degradation mechanism of each claw surface is not clear.In this paper,a detailed degradation analysis was carried out on each claw surface of movable latch combined with wear result and worn morphology.Results indicate that the boundary of carbide is preferred for corrosion because carbide presents a nobler Volta potential compared to the metal matrix or boundary region.Due to the oscillation of drive shaft between the claw surfaces of movable latch,the dominant wear mechanism on the upper surface of claw(USC)and lower surface of claw(LSC)is plastic deformation caused by impact wear.Mechanical impact wear will cause the fragmentation of carbides because of the high hardness and low ductility of carbides.Corrosion promotes the broken carbides to fall off from the metal matrix.The generated fine carbides(abrasive particles)cause extra abrasive wear on USC when the movable brings the drive shaft upward or downward.As a result,USC has a higher wear volume than LSC.This research proposes a method to evaluate the wear on the whole movable latches using a 3D full-size scanner.展开更多
This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim...This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim of this actuator is to allow these instruments to become articulated with a push of a button in order to provide the optimum angulation required during SLS operations. This new actuator is comprised of electromagnetic coil elements, soft magnetic frames and a permanent magnet. Unlike conventional electromagnetic actuators, latching-type electromagnetic actuators could maintain their positions at either end of the actuation stroke without any power application requirement. In the current design, magnetic attraction forces initiated between the permanent magnet and the magnetic frame are utilised to lock the position of the actuator whilst a certain angulation position of the actuator is achieved as a result of the magnetic repulsion forces established between the permanent magnet and the coil elements. The performance of the new actuator in terms of the output force, maximum angulation and patient’s safety, was evaluated experimentally and the results were found to compare well with those acquired numerically using finite element methods. This actuator was seen to exhibit sufficient actuation forces and hence, it was capable of providing adaptable angulation characteristics for SLS tools. Finally, thermal evaluation of the actuator’s operation was conducted, which was found to be within safety limits specified by clinicians.展开更多
文摘针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。
基金The Open Project Program of the Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems(2023SZKF17)the University Synergy Innovation Program of Anhui Province(GXXT-2022-080)。
文摘With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.
基金Project supported by the National Natural Science Foundation of China(Grant No.61974017)。
文摘Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.
文摘A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.
文摘A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0. 9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply.
文摘A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.
基金The National High Technology Research and Development Program of China (863 Program) (No. 2007AA01Z2A7)Program for Special Talents in Six Fields of Jiangsu Province
文摘Based on 0.13μm complementary metal-oxide-semiconductor（CMOS） technology,a phase and frequency detector（PFD） is designed with a low supply voltage of 0.5V for frequency synthesizers used in wireless sensor networks（WSNs）.The PFD can compare the frequency and phase differences of input signals and deliver a signal voltage proportional to the difference.Low threshold transistors are used in the circuits since a power supply of 0.5V is adopted.A pulse latched structure is also used in the circuits in order to increase both the detection range of phase errors and the maximum operation frequency.In experiments,a phase error with a range from-358° to 358° is measured when the input signal frequency is 2MHz.The PFD has a faster acquisition speed compared with conventional digital PFDs.When the input signals are at a frequency of 2MHz with zero phase error,the circuits have a power consumption of 1.8[KG＊8]μW,and the maximum operation frequency is 1.25GHz.
基金Supported by Sichuan Science and Technology Program(Grant No.2019ZDZX0001)National Natural Science Foundation of China(Grant No.U2067221)Sichuan Science and Technology Planning Project(Grant No.22JCQN0111).
文摘The current research of nuclear control rod drive mechanism(CRDM)movable latch only makes a simple measurement of wear mass.The wear volume and difference in various claw surfaces are ignored and the degradation mechanism of each claw surface is not clear.In this paper,a detailed degradation analysis was carried out on each claw surface of movable latch combined with wear result and worn morphology.Results indicate that the boundary of carbide is preferred for corrosion because carbide presents a nobler Volta potential compared to the metal matrix or boundary region.Due to the oscillation of drive shaft between the claw surfaces of movable latch,the dominant wear mechanism on the upper surface of claw(USC)and lower surface of claw(LSC)is plastic deformation caused by impact wear.Mechanical impact wear will cause the fragmentation of carbides because of the high hardness and low ductility of carbides.Corrosion promotes the broken carbides to fall off from the metal matrix.The generated fine carbides(abrasive particles)cause extra abrasive wear on USC when the movable brings the drive shaft upward or downward.As a result,USC has a higher wear volume than LSC.This research proposes a method to evaluate the wear on the whole movable latches using a 3D full-size scanner.
文摘This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim of this actuator is to allow these instruments to become articulated with a push of a button in order to provide the optimum angulation required during SLS operations. This new actuator is comprised of electromagnetic coil elements, soft magnetic frames and a permanent magnet. Unlike conventional electromagnetic actuators, latching-type electromagnetic actuators could maintain their positions at either end of the actuation stroke without any power application requirement. In the current design, magnetic attraction forces initiated between the permanent magnet and the magnetic frame are utilised to lock the position of the actuator whilst a certain angulation position of the actuator is achieved as a result of the magnetic repulsion forces established between the permanent magnet and the coil elements. The performance of the new actuator in terms of the output force, maximum angulation and patient’s safety, was evaluated experimentally and the results were found to compare well with those acquired numerically using finite element methods. This actuator was seen to exhibit sufficient actuation forces and hence, it was capable of providing adaptable angulation characteristics for SLS tools. Finally, thermal evaluation of the actuator’s operation was conducted, which was found to be within safety limits specified by clinicians.
