A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift...A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.展开更多
A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS pro...A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.展开更多
The behaviors of lead zirconate titanate （PZT） deposited as the dielectric for high-voltage devices are investigated experimentally and theoretically. The devices demonstrate not only high breakdown voltages above 3...The behaviors of lead zirconate titanate （PZT） deposited as the dielectric for high-voltage devices are investigated experimentally and theoretically. The devices demonstrate not only high breakdown voltages above 350 V, but also excellent memory behaviors. A drain current–gate voltage （ID-VG） memory window of about 2.2 V is obtained at the sweep voltages of ±10 V for the 350-V laterally diffused metal oxide semiconductor （LDMOS）. The retention time of about 270 s is recorded for the LDMOS through a controlled ID-VG measurement. The LDMOS with memory behaviors has potential to be applied in future power conversion circuits to boost the performance of the energy conversion system.展开更多
A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on t...A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.展开更多
由于薄硅膜——绝缘体上硅型横向扩散金属氧化物半导体(Silicon On Insulator Laterally Diffused Metal Oxide Semiconductor,SOI LDMOS)制作在厚度仅有几十到几百纳米的硅膜上,器件在高电压、大电流的作用下,热载流子注入(Hot Carrier...由于薄硅膜——绝缘体上硅型横向扩散金属氧化物半导体(Silicon On Insulator Laterally Diffused Metal Oxide Semiconductor,SOI LDMOS)制作在厚度仅有几十到几百纳米的硅膜上,器件在高电压、大电流的作用下,热载流子注入(Hot Carrier Injection,HCI)效应更为复杂,HCI可靠性受到极大的挑战。研究并探讨了两种结构的15 V SOI LDMOS的热载流子注入劣变机理。采用电荷泵(Charge Pumping)方法测试了界面缺陷产生的特点,当HCI效应发生在沟道区,最大沟道跨导退化明显,饱和驱动电流退化幅度较小,当HCI效应发生在多晶栅边缘,情况刚好相反。通过TCAD仿真研究了器件结构和碰撞电离率分布规律,发现了碰撞电离产生的负电荷对漂移区影响机制,揭示了HCI效应即碰撞电离率最大的位置对SOI LDMOS器件的损伤机理。为薄硅膜SOI LDMOS器件的HCI可靠性设计与优化提供了重要的经验参考。展开更多
E类功率放大器（PA）具有设计简单和高效率的优点,然而频率较高时功率管的寄生输出电容大于E类功率放大器所需的电容,这个寄生输出电容导致E类功率放大器的效率降低。提出一种高频E类功率放大器的设计方法,使用负载牵引得到考虑寄生输...E类功率放大器（PA）具有设计简单和高效率的优点,然而频率较高时功率管的寄生输出电容大于E类功率放大器所需的电容,这个寄生输出电容导致E类功率放大器的效率降低。提出一种高频E类功率放大器的设计方法,使用负载牵引得到考虑寄生输出电容后的最佳负载阻抗,再结合谐波阻抗控制方法设计E类功率放大器。采用飞思卡尔的横向扩散金属氧化物半导体（LDMOS）功率管MRF21010设计了一款工作在930~960 MHz的E类功率放大器。测试数据表明,该功率放大器的输出功率为36.8 d Bm（4.79 W）,具有79.4%的功率附加效率。展开更多
基于功率放大器(PA)效率提高技术,设计了一套包络跟踪(ET)功率放大器系统,射频(RF)功率放大器的漏极采用三电位G类结构的包络跟踪放大器提供自适应电压偏置,包络放大器包含两个自主设计的横向双扩散晶体管(LDMOS)开关管,RF功率放大器采...基于功率放大器(PA)效率提高技术,设计了一套包络跟踪(ET)功率放大器系统,射频(RF)功率放大器的漏极采用三电位G类结构的包络跟踪放大器提供自适应电压偏置,包络放大器包含两个自主设计的横向双扩散晶体管(LDMOS)开关管,RF功率放大器采用自主研发的LDMOS功率放大管进行优化匹配设计。在连续波(CW)信号激励下,28 V恒定电压下测得功率放大器在2.11 GHz下饱和输出功率为40 d Bm,饱和漏极效率为51%,输出功率回退8 d B时的漏极效率为22%,采用包络跟踪后提高至40%。在8 d B峰均比(PAR)WCDMA信号激励下,28 V恒定电压下测得功率放大器的平均效率为21%,采用包络跟踪后提高至35%。实验结果表明,采用自主设计的LDMOS开关管和LDMOS功率放大管应用到包络跟踪系统后,功率放大器的效率明显提高,验证了包络跟踪技术的优势和自主设计的LDMOS管芯的优越性。展开更多
基金Project supported by the National Science and Technology Project of the Ministry of Science and Technology of China(Grant No.2010ZX02201)the National Natural Science Foundation of China(Grant No.61176069)the National Defense Pre-Research of China(Grant No.51308020304)
文摘A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.
基金supported by the National Natural Science Foundation of China(Grant No.61464003)the Guangxi Natural Science Foundation,China(Grant Nos.2015GXNSFAA139300 and 2018JJA170010)
文摘A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.
基金the National Basic Research Program of China(Grant No.50772019)the National Natural Science Foundation of China(Grant No.61204084)
文摘The behaviors of lead zirconate titanate （PZT） deposited as the dielectric for high-voltage devices are investigated experimentally and theoretically. The devices demonstrate not only high breakdown voltages above 350 V, but also excellent memory behaviors. A drain current–gate voltage （ID-VG） memory window of about 2.2 V is obtained at the sweep voltages of ±10 V for the 350-V laterally diffused metal oxide semiconductor （LDMOS）. The retention time of about 270 s is recorded for the LDMOS through a controlled ID-VG measurement. The LDMOS with memory behaviors has potential to be applied in future power conversion circuits to boost the performance of the energy conversion system.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 60976060)the National Key Laboratory of Analogue Integrated Circuit, China (Grant No. 9140C090304110C0905)
文摘A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.
文摘由于薄硅膜——绝缘体上硅型横向扩散金属氧化物半导体(Silicon On Insulator Laterally Diffused Metal Oxide Semiconductor,SOI LDMOS)制作在厚度仅有几十到几百纳米的硅膜上,器件在高电压、大电流的作用下,热载流子注入(Hot Carrier Injection,HCI)效应更为复杂,HCI可靠性受到极大的挑战。研究并探讨了两种结构的15 V SOI LDMOS的热载流子注入劣变机理。采用电荷泵(Charge Pumping)方法测试了界面缺陷产生的特点,当HCI效应发生在沟道区,最大沟道跨导退化明显,饱和驱动电流退化幅度较小,当HCI效应发生在多晶栅边缘,情况刚好相反。通过TCAD仿真研究了器件结构和碰撞电离率分布规律,发现了碰撞电离产生的负电荷对漂移区影响机制,揭示了HCI效应即碰撞电离率最大的位置对SOI LDMOS器件的损伤机理。为薄硅膜SOI LDMOS器件的HCI可靠性设计与优化提供了重要的经验参考。
文摘E类功率放大器（PA）具有设计简单和高效率的优点,然而频率较高时功率管的寄生输出电容大于E类功率放大器所需的电容,这个寄生输出电容导致E类功率放大器的效率降低。提出一种高频E类功率放大器的设计方法,使用负载牵引得到考虑寄生输出电容后的最佳负载阻抗,再结合谐波阻抗控制方法设计E类功率放大器。采用飞思卡尔的横向扩散金属氧化物半导体（LDMOS）功率管MRF21010设计了一款工作在930~960 MHz的E类功率放大器。测试数据表明,该功率放大器的输出功率为36.8 d Bm（4.79 W）,具有79.4%的功率附加效率。
文摘基于功率放大器(PA)效率提高技术,设计了一套包络跟踪(ET)功率放大器系统,射频(RF)功率放大器的漏极采用三电位G类结构的包络跟踪放大器提供自适应电压偏置,包络放大器包含两个自主设计的横向双扩散晶体管(LDMOS)开关管,RF功率放大器采用自主研发的LDMOS功率放大管进行优化匹配设计。在连续波(CW)信号激励下,28 V恒定电压下测得功率放大器在2.11 GHz下饱和输出功率为40 d Bm,饱和漏极效率为51%,输出功率回退8 d B时的漏极效率为22%,采用包络跟踪后提高至40%。在8 d B峰均比(PAR)WCDMA信号激励下,28 V恒定电压下测得功率放大器的平均效率为21%,采用包络跟踪后提高至35%。实验结果表明,采用自主设计的LDMOS开关管和LDMOS功率放大管应用到包络跟踪系统后,功率放大器的效率明显提高,验证了包络跟踪技术的优势和自主设计的LDMOS管芯的优越性。
