A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge...A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.展开更多
A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS pro...A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.展开更多
由于薄硅膜——绝缘体上硅型横向扩散金属氧化物半导体(Silicon On Insulator Laterally Diffused Metal Oxide Semiconductor,SOI LDMOS)制作在厚度仅有几十到几百纳米的硅膜上,器件在高电压、大电流的作用下,热载流子注入(Hot Carrier...由于薄硅膜——绝缘体上硅型横向扩散金属氧化物半导体(Silicon On Insulator Laterally Diffused Metal Oxide Semiconductor,SOI LDMOS)制作在厚度仅有几十到几百纳米的硅膜上,器件在高电压、大电流的作用下,热载流子注入(Hot Carrier Injection,HCI)效应更为复杂,HCI可靠性受到极大的挑战。研究并探讨了两种结构的15 V SOI LDMOS的热载流子注入劣变机理。采用电荷泵(Charge Pumping)方法测试了界面缺陷产生的特点,当HCI效应发生在沟道区,最大沟道跨导退化明显,饱和驱动电流退化幅度较小,当HCI效应发生在多晶栅边缘,情况刚好相反。通过TCAD仿真研究了器件结构和碰撞电离率分布规律,发现了碰撞电离产生的负电荷对漂移区影响机制,揭示了HCI效应即碰撞电离率最大的位置对SOI LDMOS器件的损伤机理。为薄硅膜SOI LDMOS器件的HCI可靠性设计与优化提供了重要的经验参考。展开更多
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201)the National Natural Science Foundation of China (Grant No. 61176069)the National Defense Pre-Research of China (Grant No. 51308020304)
文摘A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.
基金supported by the National Natural Science Foundation of China(Grant No.61464003)the Guangxi Natural Science Foundation,China(Grant Nos.2015GXNSFAA139300 and 2018JJA170010)
文摘A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.
文摘由于薄硅膜——绝缘体上硅型横向扩散金属氧化物半导体(Silicon On Insulator Laterally Diffused Metal Oxide Semiconductor,SOI LDMOS)制作在厚度仅有几十到几百纳米的硅膜上,器件在高电压、大电流的作用下,热载流子注入(Hot Carrier Injection,HCI)效应更为复杂,HCI可靠性受到极大的挑战。研究并探讨了两种结构的15 V SOI LDMOS的热载流子注入劣变机理。采用电荷泵(Charge Pumping)方法测试了界面缺陷产生的特点,当HCI效应发生在沟道区,最大沟道跨导退化明显,饱和驱动电流退化幅度较小,当HCI效应发生在多晶栅边缘,情况刚好相反。通过TCAD仿真研究了器件结构和碰撞电离率分布规律,发现了碰撞电离产生的负电荷对漂移区影响机制,揭示了HCI效应即碰撞电离率最大的位置对SOI LDMOS器件的损伤机理。为薄硅膜SOI LDMOS器件的HCI可靠性设计与优化提供了重要的经验参考。
