A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS pro...A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.展开更多
A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift...A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.展开更多
We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopa...We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height （SBH） for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.展开更多
In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and ...In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and characterized by photoluminescence spectra（PL）,x-ray diffraction（XRD）,and x-ray photoelectron spectroscopy（XPS）.With PCBM layers,the current–voltage hysteresis phenomenon is effetely inhibited,and both the transfer and output current values increase.The band energy diagrams are proposed,which indicate that the electrons are transferred into the PCBM layer,resulting in the increase of photocurrent.The electron mobility and hole mobility are extracted from the transfer curves,which are about one order of magnitude as large as those of PCBM deposited,which is the reason why the electrons are transferred into the PCBM layer and the holes are still in the perovskites,and the effects of ionized impurity scattering on carrier transport become smaller.展开更多
A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based ...A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.展开更多
Subthreshold characteristics of vertical tunneling field effect transistors（VTFETs） with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three ...Subthreshold characteristics of vertical tunneling field effect transistors（VTFETs） with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations.Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET.This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region,depending on the turn-on sequence of these two components.To our knowledge,this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid.Our results indicate that the design of the nC pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.展开更多
This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to imp...This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.展开更多
Carbon nanotubes(CNTs)are ideal candidates for beyond-silicon nano-electronics because of their high mobility and low-cost processing.Recently,assembled massively aligned CNTs have emerged as an important platform for...Carbon nanotubes(CNTs)are ideal candidates for beyond-silicon nano-electronics because of their high mobility and low-cost processing.Recently,assembled massively aligned CNTs have emerged as an important platform for semiconductor electronics.However,realizing sophisticated complementary nano-electronics has been challenging due to the p-type nature of carbon nanotubes in air.Fabrication of n-type behavior field effect transistors(FETs)based on assembled aligned CNT arrays is needed for advanced CNT electronics.Here in this paper,we report a scalable process to make n-type behavior FETs based on assembled aligned CNT arrays.Air-stable and high-performance n-type behavior CNT FETs are achieved with high yield by combining the atomic layer deposition dielectric and metal contact engineering.We also systematically studied the contribution of metal contacts and atomic layer deposition passivation in determining the transistor polarity.Based on these experimental results,we report the successful demonstration of complementary metal-oxide-semiconductor inverters with good performance,which paves the way for realizing the promising future of carbon nanotube nano-electronics.展开更多
The physical mechanisms triggering electrostatic discharge （ESD） in high voltage LDMOS power transistors （〉 160 V） under transmission line pulsing （TLP） and very fast transmission line pulsing （VFTLP） stress ...The physical mechanisms triggering electrostatic discharge （ESD） in high voltage LDMOS power transistors （〉 160 V） under transmission line pulsing （TLP） and very fast transmission line pulsing （VFTLP） stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.展开更多
基金supported by the National Natural Science Foundation of China(Grant No.61464003)the Guangxi Natural Science Foundation,China(Grant Nos.2015GXNSFAA139300 and 2018JJA170010)
文摘A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.
基金Project supported by the National Science and Technology Project of the Ministry of Science and Technology of China(Grant No.2010ZX02201)the National Natural Science Foundation of China(Grant No.61176069)the National Defense Pre-Research of China(Grant No.51308020304)
文摘A novel low specific on-resistance （Ron,sp） lateral double-diffused metal oxide semiconductor （LDMOS） with a buried improved super-junction （BISJ） layer is proposed. A super-junction layer is buried in the drift region and the P pillar is split into two parts with different doping concentrations. Firstly, the buried super-junction layer causes the multiple-direction assisted depletion effect. The drift region doping concentration of the BISJ LDMOS is therefore much higher than that of the conventional LDMOS. Secondly, the buried super-junction layer provides a bulk low on-resistance path. Both of them reduce Ron,sp greatly. Thirdly, the electric field modulation effect of the new electric field peak introduced by the step doped P pillar improves the breakdown voltage （BV）. The BISJ LDMOS exhibits a BV of 300 V and Ron,sp of 8.08 mΩ·cm2 which increases BV by 35% and reduces Ron,sp by 60% compared with those of a conventional LDMOS with a drift length of 15 μm, respectively.
基金Supported by the National Natural Science Foundation of China under Grant No 61674161the Open Project of State Key Laboratory of Functional Materials for Informatics
文摘We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height （SBH） for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.
基金Project supported by the National Natural Science Foundation of China(Grant No.51602241)the China Postdoctoral Science Foundation(Grant No.2016M592754)
文摘In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and characterized by photoluminescence spectra（PL）,x-ray diffraction（XRD）,and x-ray photoelectron spectroscopy（XPS）.With PCBM layers,the current–voltage hysteresis phenomenon is effetely inhibited,and both the transfer and output current values increase.The band energy diagrams are proposed,which indicate that the electrons are transferred into the PCBM layer,resulting in the increase of photocurrent.The electron mobility and hole mobility are extracted from the transfer curves,which are about one order of magnitude as large as those of PCBM deposited,which is the reason why the electrons are transferred into the PCBM layer and the holes are still in the perovskites,and the effects of ionized impurity scattering on carrier transport become smaller.
基金the Major Science and Technology Program of Anhui Province under Grant No.2020b05050007.
文摘A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.
基金supported in part by the National Natural Science Foundation of China(52105589 and U1909221)in part by the China Postdoctoral Science Foundation(2021M692590)+2 种基金in part by the Beijing Advanced Innovation Center for Intelligent Robots and Systems(2019IRS08)in part by the Fundamental Research Funds for the Central Universities(China)(xzy012021009)in part by the State Key Laboratory of Robotics and Systems(HIT)(SKLRS2021KF17)。
基金Project supported by the International Research Training Group
文摘Subthreshold characteristics of vertical tunneling field effect transistors（VTFETs） with an nC-pocket in the pC-source are studied by simulating the transfer characteristics with a commercial device simulator.Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations.Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET.This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region,depending on the turn-on sequence of these two components.To our knowledge,this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid.Our results indicate that the design of the nC pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.
文摘This paper proposes a laterally graded junctionless transistor taking peak doping concentration near the source and drain region, and a gradual decrease in doping concentration towards the center of the channel to improve the I OFF and I ON/I OFF ratio. The decrease of doping concentration in the lateral direction of the channel region depletes a greater number of charge carriers compared to the uniformly doped channel in the OFF-state,which in turn suppresses the OFF state current flowing through the device without greatly affecting the ON state current.
基金support from National Science Foundation(NSF)via SNM-IS Award(No.1727523)。
文摘Carbon nanotubes(CNTs)are ideal candidates for beyond-silicon nano-electronics because of their high mobility and low-cost processing.Recently,assembled massively aligned CNTs have emerged as an important platform for semiconductor electronics.However,realizing sophisticated complementary nano-electronics has been challenging due to the p-type nature of carbon nanotubes in air.Fabrication of n-type behavior field effect transistors(FETs)based on assembled aligned CNT arrays is needed for advanced CNT electronics.Here in this paper,we report a scalable process to make n-type behavior FETs based on assembled aligned CNT arrays.Air-stable and high-performance n-type behavior CNT FETs are achieved with high yield by combining the atomic layer deposition dielectric and metal contact engineering.We also systematically studied the contribution of metal contacts and atomic layer deposition passivation in determining the transistor polarity.Based on these experimental results,we report the successful demonstration of complementary metal-oxide-semiconductor inverters with good performance,which paves the way for realizing the promising future of carbon nanotube nano-electronics.
文摘The physical mechanisms triggering electrostatic discharge （ESD） in high voltage LDMOS power transistors （〉 160 V） under transmission line pulsing （TLP） and very fast transmission line pulsing （VFTLP） stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.
