An analytical evaluation method for output waveform quality of space vector pulse width modulation(PWM)strategies applied in neutral⁃point⁃clamped three⁃level converter(3L⁃NPC)is proposed in this paper.Low frequency e...An analytical evaluation method for output waveform quality of space vector pulse width modulation(PWM)strategies applied in neutral⁃point⁃clamped three⁃level converter(3L⁃NPC)is proposed in this paper.Low frequency error caused by neutral point voltage ripple and high frequency error introduced by space vector synthesis were both taken into account,and the unified error model of output current ripple was established.By taking continuous and discontinuous modulation strategies as examples,the unified error model was validated through Fourier analysis of the experimental results.The proposed evaluation method will be helpful for the switching sequence optimization and the modulation strategy selection.展开更多
Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are ...Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.展开更多
基金National Natural Science Foundation of China(Grant Nos.51807140 and 51690183).
文摘An analytical evaluation method for output waveform quality of space vector pulse width modulation(PWM)strategies applied in neutral⁃point⁃clamped three⁃level converter(3L⁃NPC)is proposed in this paper.Low frequency error caused by neutral point voltage ripple and high frequency error introduced by space vector synthesis were both taken into account,and the unified error model of output current ripple was established.By taking continuous and discontinuous modulation strategies as examples,the unified error model was validated through Fourier analysis of the experimental results.The proposed evaluation method will be helpful for the switching sequence optimization and the modulation strategy selection.
基金Supported by the National Natural Science Foundation of China （No.60503027） Acknowledgements： The authors are grateful to Prof. Zhao PeiYi of Chapman University, Orange, USA, for beneficial discussions.
文摘Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.
