Aiming at the problem that existing models in aspect-level sentiment analysis cannot fully and effectively utilize sentence semantic and syntactic structure information, this paper proposes a graph neural network-base...Aiming at the problem that existing models in aspect-level sentiment analysis cannot fully and effectively utilize sentence semantic and syntactic structure information, this paper proposes a graph neural network-based aspect-level sentiment classification model. Self-attention, aspectual word multi-head attention and dependent syntactic relations are fused and the node representations are enhanced with graph convolutional networks to enable the model to fully learn the global semantic and syntactic structural information of sentences. Experimental results show that the model performs well on three public benchmark datasets Rest14, Lap14, and Twitter, improving the accuracy of sentiment classification.展开更多
Partitioning is a fundamental problem with applications to many areas including data mining, parellel processing and Very-large-scale integration （VLSI） design. An effective multi-level algorithm for bisecting graph...Partitioning is a fundamental problem with applications to many areas including data mining, parellel processing and Very-large-scale integration （VLSI） design. An effective multi-level algorithm for bisecting graph is proposed. During its coarsening phase, an improved matching approach based on the global information of the graph core is developed with its guidance function. During the refinement phase, the vertex gain is exploited as ant＇s heuristic information and a positive feedback method based on pheromone trails is used to find the global approximate bipartitioning. It is implemented with American National Standards Institute （ANSI） C and compared to MeTiS. The experimental evaluation shows that it performs well and produces encouraging solutions on 18 different graphs benchmarks.展开更多
Segmentation of three-dimensional(3D) complicated structures is of great importance for many real applications.In this work we combine graph cut minimization method with a variant of the level set idea for 3D segmenta...Segmentation of three-dimensional(3D) complicated structures is of great importance for many real applications.In this work we combine graph cut minimization method with a variant of the level set idea for 3D segmentation based on the Mumford-Shah model.Compared with the traditional approach for solving the Euler-Lagrange equation we do not need to solve any partial differential equations.Instead,the minimum cut on a special designed graph need to be computed.The method is tested on data with complicated structures.It is rather stable with respect to initial value and the algorithm is nearly parameter free.Experiments show that it can solve large problems much faster than traditional approaches.展开更多
The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timi...The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.展开更多
文摘Aiming at the problem that existing models in aspect-level sentiment analysis cannot fully and effectively utilize sentence semantic and syntactic structure information, this paper proposes a graph neural network-based aspect-level sentiment classification model. Self-attention, aspectual word multi-head attention and dependent syntactic relations are fused and the node representations are enhanced with graph convolutional networks to enable the model to fully learn the global semantic and syntactic structural information of sentences. Experimental results show that the model performs well on three public benchmark datasets Rest14, Lap14, and Twitter, improving the accuracy of sentiment classification.
基金the International Cooperation Project of Ministry of Science and Technology of P. R. China (GrantNo.CB7-2-01)SEC E-Institute: Shanghai High Institutions Grid
文摘Partitioning is a fundamental problem with applications to many areas including data mining, parellel processing and Very-large-scale integration （VLSI） design. An effective multi-level algorithm for bisecting graph is proposed. During its coarsening phase, an improved matching approach based on the global information of the graph core is developed with its guidance function. During the refinement phase, the vertex gain is exploited as ant＇s heuristic information and a positive feedback method based on pheromone trails is used to find the global approximate bipartitioning. It is implemented with American National Standards Institute （ANSI） C and compared to MeTiS. The experimental evaluation shows that it performs well and produces encouraging solutions on 18 different graphs benchmarks.
基金support from the Centre for Integrated Petroleum Research(CIPR),University of Bergen, Norway,and Singapore MOE Grant T207B2202NRF2007IDMIDM002-010
文摘Segmentation of three-dimensional(3D) complicated structures is of great importance for many real applications.In this work we combine graph cut minimization method with a variant of the level set idea for 3D segmentation based on the Mumford-Shah model.Compared with the traditional approach for solving the Euler-Lagrange equation we do not need to solve any partial differential equations.Instead,the minimum cut on a special designed graph need to be computed.The method is tested on data with complicated structures.It is rather stable with respect to initial value and the algorithm is nearly parameter free.Experiments show that it can solve large problems much faster than traditional approaches.
文摘The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.
