A new high-voltage level-shifting circuit for half-bridge power ICs

In order to reduce the chip area and improve the reliability of HVICs, a new high-voltage level-shifting circuit with an integrated low-voltage power supply, two PMOS active resistors and a current mirror is proposed. The integrated low-voltage power supply not only provides energy for the level-shifting circuit and the logic circuit, but also provides voltage signals for the gates and sources of the PMOS active resistors to ensure that they are normally-on. The normally-on PMOS transistors do not, therefore, need to be fabricated in the depletion process. The current mirror ensures that the level-shifting circuit has a constant current, which can reduce the process error of the high-voltage devices of the circuit. Moreover, an improved RS trigger is also proposed to improve the reliability of the circuit. The proposed level-shifting circuit is analyzed and confirmed by simulation with MEDICI, and the simulation results show that the function is achieved well.

A new level-shifting structure with multiply metal rings by divided RESURF technique

A new structure of a lateral n-MOST and a new level-shifting structure with multiply metal rings （MMRs） by divided RESURF technique have been proposed. The device and electrical performances of the structure are analyzed and simulated by MEDICI. In comparison to the level-shifting structure with multiply floating field plates （MFFPs） used before, the structure stated here improves the reliability and diminishes the voltage difference between the voltage of the power supply of the high-side gate driver and the voltage of the output terminal of the level-shifting structure, which is also that of the input terminal of the high-side gate driver. The maximal voltage difference of the level-shifting structure in this paper is 30% lower than that used before. Therefore, good voltage isolation and current isolation are obtained. The structure can be used in the level-shifting circuit of various applications.

A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

A new quasi-three-dimensional （quasi-3D） numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.

New Level-Shift LDMOS Structure for a 600 V-HVIC on Thick SOl

A novel level-shift LDMOS （lateral double-diffused metal oxide semiconductor） structure with the HV （high voltage） -interconnection for a 600 V-HVIC （high voltage integrated circuit） on thick SOI （silicon on insulator） is proposed. There are two original points in the proposed structure. One is the formation of the double floating p-layers under the HV-interconnection to prevent potential distribution in the drift from disturbing due to the HV-interconnection, and the other is a good combination between the LDMOS structure and multiple trench isolation to obtain the isolation performance over 600 V. From the proposed structure, the high blocking capability of the LDMOS, including both off- and on-breakdown voltages over 600 V and high hot carrier instability, and the isolation performance over 1,200 V can be obtained successfully. This paper will show numerical and experimental results in detail.