A 12 Gbit/s limiting amplifier using 2 GaAs HBT technology for fiber-optic transmission system

A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.

5Gb/s 0.25μm CMOS Limiting Amplifier

A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.

A 155Mbps 0.5μm CMOS Limiting Amplifier

This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer, and a DC offset cancellation feedback loop. The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor. The chip was packaged before being tested. The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV. Its output eye diagram remains satisfactory when the pseudo-random bit sequence （PRBS） input speed reaches 400Mbps.

Design of 15 Gb/s inductorless limiting amplifier with RSSI and LOS indication in 65nm CMOS

A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed op- tical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. The re- ceiver signal strength indictor （RSSI） can detect input signal power with 33dB dynamic range, and the limiting amplifier features a programmable loss of signal （LOS） indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER = 10^ -12 and the layout area is only 0.53 × 0.72 mm^2 because of no passive inductor. The total gain is over 41dB, and bandwidth exceeds 12GHz with 56mW power dissipation.

Low-Noise Amplification, Detection and Spectroscopy of Ultra-Cold Systems in RF Cavities

The design and development of a cryogenic Ultra-Low-Noise Signal Amplification (ULNA) and detection system for spectroscopy of ultra-cold systems are reported here for the operation in the 0.5 - 4 GHz spectrum of frequencies (the “L” and “S” microwave bands). The design is suitable for weak RF signal detection and spectroscopy from ultra-cold systems confined in cryogenic RF cavities, as entailed in a number of physics, physical chemistry and analytical chemistry applications, such as NMR/NQR/EPR and microwave spectroscopy, Paul traps, Bose-Einstein Condensates (BEC’s) and cavity Quantum Electrodynamics (cQED). Using a generic Low-Noise Amplifier (LNA) architecture for a GaAs enhancement mode High-Electron Mobility FET device, our design has especially been devised for scientific applications where ultra-low-noise amplification systems are sought to amplify and detect weak RF signals under various conditions and environments, including cryogenic temperatures, with the least possible noise susceptibility. The amplifier offers a 16 dB gain and a 0.8 dB noise figure at 2.5 GHz, while operating at room temperature, which can improve significantly at low temperatures. Both dc and RF outputs are provided by the amplifier to integrate it in a closed-loop or continuous-wave spectroscopy system or connect it to a variety of instruments, a factor which is lacking in commercial LNA devices. Following the amplification stage, the RF signal detection is carried out with the help of a post-amplifier and detection system based upon a set of Zero-Bias Schottky Barrier Diodes (ZBD’s) and a high-precision ultra-low noise jFET operational amplifier. The scheme offers unique benefits of sensitive detection and very-low noise amplification for measuring extremely weak on-resonance signals with substantial low- noise response and excellent stability while eliminating complicated and expensive heterodyne schemes. The LNA stage is fully capable to be a part of low-temperature experiments while being operated in cryogenic conditions down to about 500 mK.

A Wide-Band Low Noise Amplifier for Terrestrial and Cable Receptions

We present the design of a wide-band low-noise amplifier （LNA） implemented in 0.35μm SiGe BiCMOS technology for cable and terrestrial tuner applications. The LNA utilizes current injection to achieve high linearity. Without using inductors, the LNA achieves 0.1 ～ 1GHz wide bandwidth and 18. 8dB gain with less than 1.4dB of gain variation. The noise figure of the wideband LNA is 5dB, and its 1dB compression point is - 2dBm and IIP3 is 8dBm. The LNA dissipates 120mW of power with a 5V supply.

A Low-Noise Readout Circuit for Gyroscopes

In order to suppress the noise of gyroscopes,the method based on lock-in amplifier and capacitor matching of the low-noise readout circuit is proposed. Firstly,the principle to suppress the noise by lock-in amplifier is analyzed,and the noise model of front end is proposed. Secondly,the noise optimization for the charge amplifier is presented according to the noise model of front end. Finally,a readout circuit is constructed by this approach. The measurement results show that the parasitic capacitance of front end is 18 p F,and the noise at resonant frequency( 4 k Hz) is 133 n V / Hz1 / 2,and the overall bias stability is 30° /h,and the noise level is 0. 003° /( s·Hz1 / 2). The noise of the gyroscope with the low-noise readout by this method is suppressed effectively.

A single-to-differential low-noise amplifier with low differential output imbalance

This paper presents a single-ended input differential output low-noise amplifier intended for GPS applications. We propose a method to reduce the gain/amplitude and phase imbalance of a differential output exploiting the inductive coupling of a transformer or center-tapped differential inductor.A detailed analysis of the theory of imbalance reduction,as well as a discussion on the principle of choosing the dimensions of a transformer,are given.An LNA has been implemented using TSMC 0.18μm technology with ESD-protected.Measurement on board shows a voltage gain of 24.6 dB at 1.575 GHz and a noise figure of 3.2 dB.The gain imbalance is below 0.2 dB and phase imbalance is less than 2 degrees.The LNA consumes 5.2 mA from a 1.8 V supply.

A9.8-30.1GHzCMOSlow-noise amplifier with a 3.2-dB noise figure using inductor-and transformer-based gm-boosting techniques

A 9.8–30.1 GHz CMOS low-noise amplifier(LNA)with a 3.2-dB minimum noise figure(NF)is presented.At the architecture level,a topology based on common-gate(CG)cascading with a common-source(CS)amplifier is proposed for simultaneous wideband input matching and relatively high gain.At the circuit level,multiple techniques are proposed to improve LNA performance.First,in the CG stage,loading effect is properly used instead of the conventional feedback technique,to enable simultaneous impedance and noise matching.Second,based on in-depth theoretical analysis,the inductor-and transformer-based gm-boosting techniques are employed for the CG and CS stages,respectively,to enhance the gain and reduce power consumption.Third,the floating-body method,which was originally proposed to lower NF in CS amplifiers,is adopted in the CG stage to further reduce NF.Fabricated in a 65-nm CMOS technology,the LNA chip occupies an area of only 0.2 mm^(2)and measures a maximum power gain of 10.9 dB with−3 dB bandwidth from 9.8 to 30.1 GHz.The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth.The LNA consumes 15.6 mW from a 1.2-V supply.

Design and analysis of a UWB low-noise amplifier in the 0.18μm CMOS process

An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW （without output buffer for measurement） with a 1.8 V power supply and occupies 0.88 mm^2.

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier（VG-LNA） for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA＇s input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB（-3.3 dB to 21.7 dB） variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.

A Multi-Section Quantum-Dot Semiconductor Optical Amplifier for Ultrabroad-Band Gain-Flattened Low-Noise Amplification

We propose an ultrabroad-band 1R regenerator utilizing a multi-section quantum-dot semiconductor optical amplifier. Due to the reduced electron states, quantum dot is beneficial in broadening the gain spectrum and lowering the noise figure. Combining this with a multi-section structure drastically improves the gain equality among the different bound states, leading to an increase in the maximum output power and an improvement of the noise figure.

S波段GaAs超低噪声限幅低噪声放大器芯片的研制

本文将限幅器嵌入到了低噪声放大器的输入级匹配电路,使得整体限幅放大电路的噪声系数为低噪声放大器的最小噪声系数而不需再加上限幅器的损耗,从而有效降低了整体限幅低噪声放大器的噪声系数。在此基础上,设计并实现了一款S波段限幅低噪声放大器芯片,实现了超低噪声与高耐功率的性能。测试结果表明,该款芯片在目前相近频段所有限幅低噪声放大器产品中噪声系数最小。在2.7 GHz~3.5 GHz工作频带内,实测噪声系数NF≤0.85 dB,增益≥29 dB,带内增益平坦度≤±0.3 dB,静态工作电流≤25 mA,1 dB压缩点输出功率≥8 dBm。在耐功率50 W(250μs脉宽、25%占空比)下试验30 min后不烧毁,恢复到常温时,噪声几乎无变化。芯片尺寸为3450μm×1600μm×100μm。

Design and analysis of 20 Gb/s inductorless limiting amplifier in 65 nm CMOS technology

A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.

Link Budget and Enhanced Communication Distance for Ambient Internet of Things

Backscatter communications will play an important role in connecting everything for beyond 5G(B5G)and 6G systems.One open challenge for backscatter communications is that the signals suffer a round-trip path loss so that the communication distance is short.In this paper,we first calculate the communication distance upper bounds for both uplink and downlink by measuring the tag sensitivity and reflection coefficient.It is found that the activation voltage of the envelope detection diode of the downlink tag is the main factor limiting the back-scatter communication distance.Based on this analysis,we then propose to implement a low-noise amplifier(LNA)module before the envelope detection at the tag to enhance the incident signal strength.Our experimental results on the hardware platform show that our method can increase the downlink communication range by nearly 20 m.

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC（optoelectronic integrated circuit）optical receiver front-end has been studied and fabricated based on theφ-76 mm GaAs PHEMT process;this is the first time that a limiting amplifier（LA）has been designed and realized using depletion mode PHEMT.An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier（TIA）has been established and optimized by simu- lation software ATLAS.The photodiode has a bandwidth of 10 GHz,a capacitance of 3 fF/μm and a photosensitive area of 50×50μm^2.The whole chip has an area of 1511×666μm^2.The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS.The chip area is 1950×1910μm^2 and the measured results demonstrate an input dynamic range of 34 dB（10–500 mVpp）with constant output swing of 500 mVpp.

Approaching Quantum-Limited Amplification with Large Gain Catalyzed by Optical Parametric Amplifier Medium

Amplifier is at the heart of experiments carrying out the precise measurement of a weak signal. An idea quantum amplifier should have a large gain and minimum added noise simultaneously. Here, we consider the quantum measurement properties of the cavity with the OPA medium in the op-amp mode to amplify an input signal. We show that our nonlinear-cavity quantum amplifier has large gain in the single-value stable regime and achieves quantum limit unconditionally.

Design of an OP-AMP Based on a LDO Regulator

An operational amplifier （OP-AMP） with a ground current of about 0.6μA is presented. Moreover, this amplifier reaps the benefits of incorporating a foldback current limiting circuit,which enables the low-dropout voltage regulator without the need of a special current limiting subblock. Therefore,the object of ultra-low power is realized because of a great reduction in transistors and current limbs.

一种新型真对数放大器的研究

介绍了传统真对数放大器的两种实现方式:双增益真对数放大器、并联求和真对数放大器。对这两种真对数放大器的不足进行了分析,并提出了一种基于连续检波式对数放大器、限幅放大器和乘法器的新型真对数放大器实现方法。测试结果表明,该新型真对数放大器的动态范围达88dB(±1dB误差)/76dB(±0.5dB误差),整个电路功耗为0.25 W。

2.5Gbit/sCMOS光接收机限幅放大器

给出了一个利用 0 .35 μmCMOS工艺实现的 2 .5Gb/s限幅放大器。在标准的 5V电源电压 ,功耗为 2 2 5mW。在 4 0dB的输入动态范围内 ,可以保持 4 0 0mVp p恒定输出摆幅。整个芯片面积为 1× 1 1mm2 。