A 12 Gbit/s limiting amplifier using 2 GaAs HBT technology for fiber-optic transmission system

A 12 Gbit/s limiting amplifier for fiber-optic transmission system is realized in a 2μm GaAs HBT technology. The whole circuit consists of an input buffer, three similar amplifier cells, an output buffer for driving 50 ft transmission lines and a pair of feedback networks for offset cancellation. At a positive supply voltage of 2 V and a negative supply voltage of - 2V, the power dissipation is about 280 mW. The small-signal gain is higher than 46 dB and the input dynamic range is about 40 dB with a constant single-ended output voltage swing of 400 mV. Satisfactory eye-diagrams are obtained at the bit rate of 12 Gbit/s limited by the test set-up. The chip area is 1.15 mm ×0.7 mm.

5Gb/s 0.25μm CMOS Limiting Amplifier

A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.

A 155Mbps 0.5μm CMOS Limiting Amplifier

This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer, and a DC offset cancellation feedback loop. The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor. The chip was packaged before being tested. The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV. Its output eye diagram remains satisfactory when the pseudo-random bit sequence （PRBS） input speed reaches 400Mbps.

Design of 15 Gb/s inductorless limiting amplifier with RSSI and LOS indication in 65nm CMOS

A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed op- tical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. The re- ceiver signal strength indictor （RSSI） can detect input signal power with 33dB dynamic range, and the limiting amplifier features a programmable loss of signal （LOS） indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER = 10^ -12 and the layout area is only 0.53 × 0.72 mm^2 because of no passive inductor. The total gain is over 41dB, and bandwidth exceeds 12GHz with 56mW power dissipation.

Design and analysis of 20 Gb/s inductorless limiting amplifier in 65 nm CMOS technology

A high speed inductorless limiting amplifier （LA） in an optical communication receiver with the work- ing speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation （DCOC）. It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45 × 0.25 mm2 （without PAD）. The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sddlm and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC（optoelectronic integrated circuit）optical receiver front-end has been studied and fabricated based on theφ-76 mm GaAs PHEMT process;this is the first time that a limiting amplifier（LA）has been designed and realized using depletion mode PHEMT.An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier（TIA）has been established and optimized by simu- lation software ATLAS.The photodiode has a bandwidth of 10 GHz,a capacitance of 3 fF/μm and a photosensitive area of 50×50μm^2.The whole chip has an area of 1511×666μm^2.The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS.The chip area is 1950×1910μm^2 and the measured results demonstrate an input dynamic range of 34 dB（10–500 mVpp）with constant output swing of 500 mVpp.

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

A fully integrated 40 Gbit/s optical receiver analog front-end （AFE） including a transimpedance amplifier （TIA） and a limiting amplifier （LA） for short distance communication is described in this paper. The proposed TIA employs a modified regulated cascode （RGC） configuration as input stage, and adopts a third order interleaving active feedback gain stage. The LA utilizes nested active feedback, negative capacitance, and inductor peaking technology to achieve high voltage gain and wide bandwidth. The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV（p-p）. Simulation results show that the receiver AFE provides conversion gain of up to 83 dBΩ and bandwidth of 34.7 GHz, and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA（rms）.

A 5 Gb/s CMOS adaptive equalizer for serial link

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference （ISI） for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.