A new high-voltage LDMOS with linearly-distanced fixed charge islands is proposed （LFI LDMOS）. A lot of linearly-distanced fixed charge islands are introduced by implanting the Cs or I ion into the buried oxide laye...A new high-voltage LDMOS with linearly-distanced fixed charge islands is proposed （LFI LDMOS）. A lot of linearly-distanced fixed charge islands are introduced by implanting the Cs or I ion into the buried oxide layer and dynamic holes are attracted and accumulated, which is crucial to enhance the electric field of the buried oxide and the vertical breakdown voltage. The surface electric field is improved by increasing the distance between two adjacent fixed charge islands from source to drain, which lead to the higher concentration of the drift region and a lower on-resistance. The numerical results indicate that the breakdown voltage of 500 V with Ld = 45μm is obtained in the proposed device in comparison to 209 V of conventional LDMOS, while maintaining low on- resistance.展开更多
基金Project supported by the Guangxi Natural Science Foundation of China(No.2013GXNSFAA019335)the Guangxi Department of Education Project(No.201202ZD041)+1 种基金the China Postdoctoral Science Foundation Project(Nos.2012M521127,2013T60566)the National Natural Science Foundation of China(Nos.61361011,61274077,61464003)
文摘A new high-voltage LDMOS with linearly-distanced fixed charge islands is proposed （LFI LDMOS）. A lot of linearly-distanced fixed charge islands are introduced by implanting the Cs or I ion into the buried oxide layer and dynamic holes are attracted and accumulated, which is crucial to enhance the electric field of the buried oxide and the vertical breakdown voltage. The surface electric field is improved by increasing the distance between two adjacent fixed charge islands from source to drain, which lead to the higher concentration of the drift region and a lower on-resistance. The numerical results indicate that the breakdown voltage of 500 V with Ld = 45μm is obtained in the proposed device in comparison to 209 V of conventional LDMOS, while maintaining low on- resistance.
