电源管理芯片在超过可承受温度范围工作时会对自身造成不同程度的损坏,过温保护电路对提高该类芯片的可靠性和鲁棒性具有重要作用。文中设计了一种具有温度过高关断和温度过低提醒等双重功能的高精度过温保护电路。利用正、负温度系数...电源管理芯片在超过可承受温度范围工作时会对自身造成不同程度的损坏,过温保护电路对提高该类芯片的可靠性和鲁棒性具有重要作用。文中设计了一种具有温度过高关断和温度过低提醒等双重功能的高精度过温保护电路。利用正、负温度系数电压对芯片温度进行实时检测,并与带隙基准电路输出端的不同基准电压分别进行比较得到4个逻辑翻转点,进而通过高精度比较器电路和迟滞逻辑电路处理后,输出迟滞逻辑信号来控制芯片的工作状态或进行温度过低提醒。基于0.18μm BCD(Bipolar-Complementary Metal Oxied Semiconductor-Double diffused Metal Oxide Semiconductor)工艺设计并完成了相关仿真验证,仿真结果表明,在电源电压范围为3.0~5.5 V时,该电路输出端的迟滞逻辑翻转信号对应的温度阈值最大偏移量在0.3℃以内,具备较高的精度,可广泛集成于各种需要过温保护功能的电源管理芯片。展开更多
This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control l...This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.展开更多
文摘电源管理芯片在超过可承受温度范围工作时会对自身造成不同程度的损坏,过温保护电路对提高该类芯片的可靠性和鲁棒性具有重要作用。文中设计了一种具有温度过高关断和温度过低提醒等双重功能的高精度过温保护电路。利用正、负温度系数电压对芯片温度进行实时检测,并与带隙基准电路输出端的不同基准电压分别进行比较得到4个逻辑翻转点,进而通过高精度比较器电路和迟滞逻辑电路处理后,输出迟滞逻辑信号来控制芯片的工作状态或进行温度过低提醒。基于0.18μm BCD(Bipolar-Complementary Metal Oxied Semiconductor-Double diffused Metal Oxide Semiconductor)工艺设计并完成了相关仿真验证,仿真结果表明,在电源电压范围为3.0~5.5 V时,该电路输出端的迟滞逻辑翻转信号对应的温度阈值最大偏移量在0.3℃以内,具备较高的精度,可广泛集成于各种需要过温保护功能的电源管理芯片。
基金supported by Qingdao Hi-image Technologies Co., Ltdin part by the NSFC of China under Grant 62174149, 61974118, 62004156the National Key R&D Program of China under Grant 2022YFC2404902
文摘This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.
