Enhanced Portable LUT Multiplier with Gated Power Optimization for Biomedical Therapeutic Devices

Digital design of a digital signal processor involves accurate and high-speed mathematical computation units.DSP units are one of the most power consuming and memory occupying devices.Multipliers are the common building blocks in most of the DSP units which demands low power and area constraints in the field of portable biomedical devices.This research works attempts multiple power reduction technique to limit the power dissipation of the proposed LUT multiplier unit.A lookup table-based multiplier has the advantage of almost constant area requirement’s irrespective to the increase in bit size of multiplier.Clock gating is usually used to reduce the unnecessary switching activities in idle circlet components.A clock tree structure is employed to enhance the SRAM based lookup table memory architecture.The LUT memory access operation is sequential in nature and instead of address decoder a ring counter is used to scan the memory contents and gated driver tree structure is implemented to control the clock and data switching activities.The proposed algorithm yields 20%of power reduction than existing.

Robust Watermarking with Kernels-Alternated Error Diffusion and Weighted Lookup Table in Halftone Images

A halftone watermarking method of high quality, robustness, and capacity flexibility is presented in this paper. An objective halftone image quality evaluation method based on the human visual system obtained by a least-mean-square algorithm is also introduced. In the encoder, the kernels-alternated error diffusion （KAEDF） is applied. It is able to maintain the computational complexity at the same level as ordinary error diffusion. Compared with Hel-Or using ordered dithering, the proposed KAEDF yields a better image quality through using error diffusion. We also propose a weighted lookup table （WLUT） in the decoder instead of lookup table （LUT）, as proposed by Pei and Guo, so as to achieve a higher decoded rate. As the experimental results demonstrate, this technique is able to guard against degradation due to tampering, cropping, rotation, and print-and-scan processes in error-diffused halftone images.

A New Timing- Driven Placement Algorithm Based on Table- Lookup Delay Model

An algorithm is presented for obtaining placements of cell\|based very large scale integrated circuits, subject to timing constraints based on table\|lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well\|known quadratic placement with bottom\|up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.

Study on An Absolute Non-Collision Hash and Jumping Table IP Classification Algorithms

In order to classify packet, we propose a novel IP classification based the non-collision hash and jumping table trie-tree (NHJTTT) algorithm, which is based on noncollision hash Trie-tree and Lakshman and Stiliadis proposing a 2-dimensional classification algorithm (LS algorithm). The core of algorithm consists of two parts: structure the non-collision hash function, which is constructed mainly based on destination/source port and protocol type field so that the hash function can avoid space explosion problem; introduce jumping table Trie-tree based LS algorithm in order to reduce time complexity. The test results show that the classification rate of NHJTTT algorithm is up to 1 million packets per second and the maximum memory consumed is 9 MB for 10 000 rules. Key words IP classification - lookup algorithm - trie-tree - non-collision hash - jumping table CLC number TN 393.06 Foundation item: Supported by the Chongqing of Posts and Telecommunications Younger Teacher Fundation (A2003-03).Biography: SHANG Feng-jun (1972-), male, Ph.D. candidate, lecture, research direction: the smart instrument and network.

Lookup Table Optimization for Sensor Linearization in Small Embedded Systems

This paper treats the problem of designing an optimal size for a lookup table used for sensor linearization. In small embedded systems the lookup table must be reduced to a minimum in order to reduce the memory footprint and intermediate table values are estimated by linear interpolation. Since interpolation introduces an estimation uncertainty that increases with the sparseness of the lookup table there is a trade-off between lookup table size and estimation precision. This work will present a theory for finding the minimum allowed size of a lookup table that does not affect the overall precision, i.e. the overall precision is determined by the lookup table entries’ precision, not by the interpolation error.

基于新型BIST的LUT测试方法研究

针对FPGA内部的LUT资源覆盖测试,提出一种新型BIST的测试方法。通过改进的LFSR实现了全地址的伪随机向量输入,利用构造的黄金模块电路与被测模块进行输出比较,实现对被测模块功能的快速测试,并在Vivado 2018.3中完成了仿真测试。通过ATE测试平台,加载设计的BIST测试向量,验证结果与仿真完全一致,仅2次配置即可实现LUT的100%覆盖率测试。此外,还构建了LUT故障注入模拟电路,人为控制被测模块的输入故障,通过新型BIST的测试方法有效诊断出被测模块功能异常,实现了准确识别。以上结果表明,该方法不仅降低了测试配置次数,而且能够准确识别LUT功能故障,适用于大规模量产测试。

Power and Time Efficient IP Lookup Table Design Using Partitioned TCAMs

This paper proposes a power and time efficient scheme for designing IP lookup tables. The proposed scheme uses partitioned Ternary Content Addressable Memories (TCAMs) that store IP lookup tables. The proposed scheme enables O(1) time penalty for updating an IP lookup table. The partitioned TCAMs allow an update done by a simple insertion without the need for routing table sorting. The organization of the routing table of the proposed scheme is based on a partition with respect to the output port for routing with a smaller priority encoder. The proposed scheme still preserves a similar storage requirement and clock rate to those of existing designs. Furthermore, this scheme reduces power consumption due to using a partitioned routing table.

WinoNet:Reconfigurable look-up table-based Winograd accelerator for arbitrary precision convolutional neural network inference

To solve the hardware deployment problem caused by the vast demanding computational complexity of convolutional layers and limited hardware resources for the hardware network inference,a look-up table(LUT)-based convolution architecture built on a field-programmable gate array using integer multipliers and addition trees is used.With the help of the Winograd algorithm,the optimization of convolution and multiplication is realized to reduce the computational complexity.The LUT-based operator is further optimized to construct a processing unit(PE).Simultaneously optimized storage streams improve memory access efficiency and solve bandwidth constraints.The data toggle rate is reduced to optimize power consumption.The experimental results show that the use of the Winograd algorithm to build basic processing units can significantly reduce the number of multipliers and achieve hardware deployment acceleration,while the time-division multiplexing of processing units improves resource utilization.Under this experimental condition,compared with the traditional convolution method,the architecture optimizes computing resources by 2.25 times and improves the peak throughput by 19.3 times.The LUT-based Winograd accelerator can effectively solve the deployment problem caused by limited hardware resources.

ARRANGING MULTICAST FORWARDING TABLE IN CLASS SEQUENCE IN TERNARY-CAM FOR LINE-SPEED LOOKUP

PIM-SM(Protocol Independent Multicast-Sparse Mode) is a main multicast routing pro-tocol in the IPv6(Internet Protocol version 6).It can use either a shared tree or a shortest path tree to deliver data packets,consequently the multicast IP lookup engine requires,in some cases,two searches to get a correct lookup result according to its multicast forwarding rule,and it may result in a new requirement of doubling the lookup speed of the lookup engine.The ordinary method to satisfy this requirement in TCAM(Ternary Content Addressable Memory) based lookup engines is to exploit parallelism among multiple TCAMs.However,traditional parallel methods always induce more re-sources and higher design difficulty.We propose in this paper a novel approach to solve this problem.By arranging multicast forwarding table in class sequence in TCAM and making full use of the intrinsic characteristic of the TCAM,our approach can get the right lookup result with just one search and a single TCAM,while keeping the hardware of lookup engine unchanged.Experimental results have shown that the approach make it possible to satisfy forwarding IPv6 multicast packets at the full link rate of 20 Gb/s with just one TCAM with the current TCAM chip.

A complete lookup table for marching cubes

The well-known marching cubes method is used to generate isosurfaces from volume data or data on a 3D rectilinear grid. To do so, it refers to a lookup table to decide on the possible configurations of the isosurface within a given cube, assuming we know whether each vertex lies inside or outside the surface. However, the vertex values alone do not uniquely determine how the isosurface may pass through the cube, and in particular how it cuts each face of the cube. Earlier lookup tables are deficient in various respects. The possible combinations of the different configurations of such ambiguous faces are used in this paper to find a complete and cor- rect lookup table. Isosurfaces generated using the new lookup table here are guaranteed to be watertight.

FPGA芯片的链结构LUT自测试方法研究

基于内建自测试(BIST)思想的FPGA测试方法利用被测芯片中的资源来构建测试所需的TPG或ORA,以减少测试对输入输出引脚和外部ATE的需求。传统的FPGA芯片BIST方法仅考虑自测试结构内被配置为CUT的资源,从而需要进行多次组测试来完成整个芯片的测试。在现有LUT自测试链结构的基础上,通过合理选择TPG的电路结构及测试配置,能够在相同测试开销下增加TPG部分的故障覆盖率,提高测试效率。

利用LUT替换的FPGA保护数字水印技术

提出一种新的基于查找表替换的IP核数字水印技术,利用基于存储式逻辑阵列块(Memory Logic ArrayBlock,MLAB)的RAM结构替换原设计文件中的查找表,在其中添加水印数据.使用此方法使嵌入的水印可以避免被优化工具删除,提高了数字水印的安全性.实验表明,此方法嵌入数字水印的效率高,资源开销较低,优于其它基于查找表的数字水印方法.

一种基于Neugebauer方程的3D_LUT均匀化方法

3D_LUT是目前普遍使用的打印机色彩校正方法,实践证明均匀3D_LUT有更高的校正精度和效率。针对3D_LUT均匀化问题,文章给出了一种先用Neugebauer方程建立打印输入/输出关系的近似描述,进而直接生成近似均匀3D_LUT的方法,并给出了对应的快速查找算法。与现有反向均匀化方法相比,新方法不附加反向插值误差,可提高色彩校正精度。

LUT数字预失真在宽带GNSS信号的应用

针对导航载荷发射链路高功率放大器非线性引起的导航信号质量与发射效率不能统一的问题,本文采用查找表数字预失真算法对北斗三号ACE BOC调制信号进行分析,该算法采用非等距线性插值基点划分来保障资源的合理划分与精度。采用导航信号功率谱及S曲线过零点偏差作为预失真前后信号质量评估准则。研究结果表明:在查找表插值基点数量固定为30时,该算法带外功率谱抑制约10~15 dB,S曲线过零点偏差由0.12 m下降至0.01 m以内。在同等S曲线过零点偏差条件下,本文方法所需插值基点数量较传统方法大幅度下降。

FAST UPDATE ALGORITHM FOR TCAM-BASED ROUTING LOOKUPS

Routing technology has been forced to evolve towards higher capacity and per port packet processing speed. The ability to achieve high forwarding speed is due to either software or hardware technology. TCAM (Ternary Content Addressable Memory) provides a performance advantage over other software or hardware search algorithms, often resulting in an order of magnitude reduction of search time. But slow updates may affect the performance of TCAM based routing lookup. So the key is to design a table management algorithm, which supports high speed updates in TCAMs. This paper presented three table management algorithms, and then compared their performance. Finally, the optimal one after comparing was given.

基于改进的LUT乘法器的FIR滤波器设计

针对目前FIR数字滤波器消耗面积较大、运行速度较慢等问题,在APC-LUT(antisymmetric product coding,APC)方法实现乘法器基础上,提出了一种改进型查找表(lookup-table,LUT)架构δ-LUT实现乘法器,省去了地址线的编码电路,控制电路简单易行;进一步,在δ-LUT的基础上,提出了改进型的LUT架构β-LUT实现乘法器,使FIR滤波器的功耗和面积等性能得到大幅度提高.进一步介绍了在输入位宽较大时通过查表操作的LUT分解方法可降低LUT的规模.采用Synopsys公司的Design Compiler,并结合TSMC 130nm的单元库,对LUT进行综合改进,结果显示,改进后的LUT实现的FIR数字滤波器,其ADP节省达60%,功耗节省达58%.

Using bidirectional links to improve peer-to-peer lookup performance

Efficient lookup is essential for peer-to-peer networks and Chord is a representative peer-to-peer lookup scheme based on distributed hash table (DHT). In peer-to-peer networks, each node maintains several unidirectional application layer links to other nodes and forwards lookup messages through such links. This paper proposes use of bidirectional links to improve the lookup performance in Chord. Every original unidirectional link is replaced by a bidirectional link, and accordingly every node becomes an anti-finger of all its finger nodes. Both theoretical analyses and experimental results indicate that these anti-fingers can help improve the lookup performance greatly with very low overhead.

基于LUT的多目机场视频实时拼接算法设计与实现

针对机场中多路实时视频信号的情况,开展了8路视频实时全景拼接的算法研究工作,基本完成了8路视频实时全景拼接算法的设计与实现。首先,借助现有全景图片合成软件,完成了图像配准,即找出每路视频图像到全景图的像素坐标映射关系;完成图像配准之后,根据像素坐标映射关系建立查找表,利用查找表,同时使用OpenMP多核并行加速,完成视频每一帧的实时拼接。相邻两路视频之间的重叠区域使用线性融合的方法进行融合。实验结果表明,该研究方法可完成8路960×540分辨率视频的实时全景拼接,得到无明显畸变全景画面。

Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach

This brief proposes an area and speed efficient implementation of symmetric finite impulse response (FIR) digital filter using reduced parallel look-up table (LUT) distributed arithmetic (DA) based approach. The complexity lying in the realization of FIR filter is dominated by the multiplier structure. This complexity grows further with filter order, which results in increased area, power, and reduced speed of operation. The speed of operation is improved over multiply-accumulate approach using multiplier less conventional DA based design and decomposed DA based design. Both the structure requires B clock cycles to get the filter output for the input width of B, which limits the speed of DA structure. This limitation is addressed using parallel LUTs, called high speed DA FIR, at the expense of additional hardware cost. With large number of taps, the number of LUTs and its size also becomes large. In the proposed method, by exploiting coefficient symmetry property, the number of LUTs in the decomposed DA form is reduced by a factor of about 2. This proposed approach is applied in high speed DA based FIR design, to obtain area and speed efficient structure. The proposed design offers around 40% less area and 53.98% less slice-delay product (SDP) than the high throughput DA based structure when it’s implemented over Xilinx Virtex-5 FPGA device-XC5VSX95T-1FF1136 for 16-tap symmetric FIR filter. The proposed design on the same FPGA device, supports up to 607 MHz input sampling frequency, and offers 60.5% more speed and 67.71% less SDP than the systolic DA based design.

Hardware Routing Lookup with SDRAMT

The authors present a routing lookup architecture, SDIR(SDRAM based Direct Index Routing). With pipeline and interleaving access technique, SDIR can provide scalable lookup speed from 16 7 MPPS(mega packet per second) to 133 MPPS with SDRAM running at 133MHz frequency.