Two new integrable couplings of the soliton hierarchies with self-consistent sources

A kind of integrable coupling of soliton equations hierarchy with self-consistent sources associated with s/（4） has been presented （Yu F J and Li L 2009 Appl. Math. Comput. 207 171; Yu F J 2008 Phys. Lett. A 372 6613）. Based on this method, we construct two integrable couplings of the soliton hierarchy with self-consistent sources by using the loop algebra sl（4）. In this paper, we also point out that there are some errors in these references and we have corrected these errors and set up new formula. The method can be generalized to other soliton hierarchy with self-consistent sources.

Fiber loop ring-down cavity integrated U-bent single-mode-fiber for magnetic field sensing

A novel magnetic field sensing system based on the fiber loop ring-down technique is proposed in this paper. In the fiber loop, a U-bent single-mode-fiber structure coated with magnetic fluid(MF) serves as the sensing head, and an erbium-doped fiber amplifier(EDFA) is introduced to compensate for the intrinsic loss of the cavity. The ring-down time of the system varies with the change of applied magnetic field due to the tunable absorption coefficient and refractive index of the MF. Therefore, measurement of the magnetic field can be realized by monitoring the ringdown time. The experimental results show that the performance of the system is extremely dependent on the interrogation wavelength, because both the gain of the EDFA and the loss of the sensing head are wavelength dependent.We found that at the optimal wavelength, the ratio of the gain to loss attained its maximum. The sensing system was experimentally demonstrated and a sensitivity of-0.5951 μs∕Oe was achieved.

Analytic two-loop master integrals for tW production at hadron colliders:Ⅰ

We present the analytic calculation of two-loop master integrals that are relevant for tW production at hadron colliders.We focus on the integral families with only one massive propagator.After selecting a canonical basis,the differential equations for the master integrals can be transformed into the d In form.The boundaries are determined by simple direct integrations or regularity conditions at kinematic points without physical singularities.The analytical results in this work are expressed in terms of multiple polylogarithms,and have been checked via numerical computations.

General one-loop reduction in generalized Feynman parametrization form

The search for an effective reduction method is one of the main topics in higher loop computation.Recently,an alternative reduction method was proposed by Chen in[1,2].In this paper,we test the power of Chen’s new method using one-loop scalar integrals with propagators of higher power.More explicitly,with the improved version of the method,we can cancel the dimension shift and terms with unwanted power shifting.Thus,the obtained integrating-by-parts relations are significantly simpler and can be solved easily.Using this method,we present explicit examples of a bubble,triangle,box,and pentagon with one doubled propagator.With these results,we complete our previous computations in[3]with the missing tadpole coefficients and show the potential of Chen’s method for efficient reduction in higher loop integrals.

A monolithic K-band phase-locked loop for microwave radar application

A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator（VCO） achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic（CML） divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency.Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components.The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of –0.84 dBm and phase noise of 91：92 d Bc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm^2 without pads under a 1.2 V single voltage supply.