A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-contr...A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator（VCO） achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic（CML） divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency.Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components.The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of –0.84 dBm and phase noise of 91：92 d Bc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm^2 without pads under a 1.2 V single voltage supply.展开更多
基金Project supported by the National High-Tech Research and Development Program of China(No.2013AA014101)
文摘A monolithic K-band phase-locked loop（PLL） for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator（VCO） achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic（CML） divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency.Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components.The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of –0.84 dBm and phase noise of 91：92 d Bc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm^2 without pads under a 1.2 V single voltage supply.
