Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout ...Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.展开更多
为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出...为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出电压经反馈网络传递给反馈端的信号耦合形成由负载电容、负载电流控制的可控零点,可有效提高LDO电路整体的稳定性。此外,电路内部加入了产生动态极点的自适应电流补偿电路以保证次极点不会对环路的相位裕度产生影响。基于0.18μm BCD工艺设计,该电路在0~800 mA的宽负载范围、5 V输入3.3 V输出下相位裕度均高于48°,适用负载电容范围≥1μF,同时该LDO在10~100 kHz的频率范围内输出噪声仅为5.0617μVrms。展开更多
This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMO...This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMOS Process.It can guarantee 150mA output current per circuit and the leakage voltage is 60mV,1nA quiescent current when both are in shutdown mode,and it has 115μA ground current,output noise is 42μVrms,130μs fast turn-on circuitry and the junction temperature range is-40℃to 125℃.展开更多
以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的...以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mV以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.展开更多
A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique...A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.展开更多
设计了一种新颖的LDO线性稳压器。该LDO工作于负电源,具有微功耗、自身固定-5V输出、外接反馈电阻可实现可调输出等特点。基于0.6μm SOI CMOS工艺进行流片。测试结果表明,该电路输入电源电压VIN为-2～-18V,可调输出电压为-1.3V～VIN+0....设计了一种新颖的LDO线性稳压器。该LDO工作于负电源,具有微功耗、自身固定-5V输出、外接反馈电阻可实现可调输出等特点。基于0.6μm SOI CMOS工艺进行流片。测试结果表明,该电路输入电源电压VIN为-2～-18V,可调输出电压为-1.3V～VIN+0.5V@IOUT=15mA。该LDO功耗低,室温下空载静态电流约4.8μA,并且几乎不随VIN变化。内部带隙电压基准采用β二阶补偿,结构简单,温度系数为1.28×10-5/℃。线性调整率为0.015%,负载调整率为0.85Ω。展开更多
基金supported by the National Natural Science Foundation of China(No.61974046)the Provincial Key Research and Development Program of Guangdong(2019B010140002)the Macao Science&Technology Development Fund(FDCT)145/2019/A3 and SKL-AMSV(UM)-2020-2022.
文摘Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.
基金This work was supported by Supported by the 2016 Annual Young Academic Leaders Scientific Research Foundation of Chengdu University of Information Technology(No.J201604)and the National Social Science Foundation(No.61504014).
文摘This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMOS Process.It can guarantee 150mA output current per circuit and the leakage voltage is 60mV,1nA quiescent current when both are in shutdown mode,and it has 115μA ground current,output noise is 42μVrms,130μs fast turn-on circuitry and the junction temperature range is-40℃to 125℃.
文摘以设计输出电流为800mA的高稳定线性稳压器(low-dropout voltage regulator,LDO)为目标,利用工作在线性区的MOS管具有压控电阻特性,构造零点跟踪电路以抵消随输出电流变化的极点,并且采用了改进型米勒补偿方案使电路系统具有60°的相位裕度,达到了大输出电流下的高稳定性要求.另外,分析了电路在转换发生时电路结构参数和负载整流特性的关系,提出了一种能在瞬间提供大电流的转换速率加强电路,达到了在负载电流从800mA到10mA跳变时,输出电压的跳变量控制在60mV以内,并且最长输出电压恢复时间在500μs以内.芯片采用CSMC公司的0.6μm CMOS数模混合信号工艺设计,并经过流片和测试,测试结果验证了设计方案.
基金Project supported by the National Natural Science Foundation of China(No60876023)
文摘A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.
文摘设计了一种新颖的LDO线性稳压器。该LDO工作于负电源,具有微功耗、自身固定-5V输出、外接反馈电阻可实现可调输出等特点。基于0.6μm SOI CMOS工艺进行流片。测试结果表明,该电路输入电源电压VIN为-2～-18V,可调输出电压为-1.3V～VIN+0.5V@IOUT=15mA。该LDO功耗低,室温下空载静态电流约4.8μA,并且几乎不随VIN变化。内部带隙电压基准采用β二阶补偿,结构简单,温度系数为1.28×10-5/℃。线性调整率为0.015%,负载调整率为0.85Ω。
文摘提出了一种集成于射频芯片的低噪声、快速建立的低压差线性稳压器(LDO)。分析了传统LDO的主要噪声源,在综合考虑芯片的噪声、静态电流和面积后,采用超低频低通滤波器,对LDO的输出噪声进行优化。基于SMIC 0.18μm工艺,采用Cadence软件对电路进行仿真。结果表明,10 Hz到100 k Hz之间的输出积分噪声电压为17μV,建立时间小于18μs,总静态电流为24μA,满足LDO的应用要求。
