For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array （FPGA）, a low-power consumption design method is proposed, which is suitable for FPGA impleme...For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array （FPGA）, a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit （IC） design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.展开更多
提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管...提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管作温度及工艺补偿感应管,利用其栅压变化控制充放电电流,使其在不同工艺角下,当温度在较大范围内变化时,均能实现输出频率稳定。采用中芯国际0.18μm工艺进行仿真验证,结果表明:当电源电压为1 V,基准电流为130 n A时,电路功耗仅为447 n W;在工艺角由ss变化到ff的过程中,输出频率偏差不超过2.43%,;温度在-40~90℃范围变化时,输出频率偏差小于0.99%,适合无源射频识别标签芯片使用。展开更多
基金supported by the Natural Science Foundation of China under Grant No.61376024 and No.61306024Natural Science Foundation of Guangdong Province under Grant No.S2013040014366Basic Research Programme of Shenzhen under Grant No.JCYJ20140417113430642 and No.JCYJ20140901003939020
文摘For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array （FPGA）, a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit （IC） design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.
文摘提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管作温度及工艺补偿感应管,利用其栅压变化控制充放电电流,使其在不同工艺角下,当温度在较大范围内变化时,均能实现输出频率稳定。采用中芯国际0.18μm工艺进行仿真验证,结果表明:当电源电压为1 V,基准电流为130 n A时,电路功耗仅为447 n W;在工艺角由ss变化到ff的过程中,输出频率偏差不超过2.43%,;温度在-40~90℃范围变化时,输出频率偏差小于0.99%,适合无源射频识别标签芯片使用。
