Increasing the Efficiency and Level of Environmental Safety of Pro-Environmental City Heat Supply Technologies by Low Power Nuclear Plants

In connection with the current prospect of decarbonization of coal energy through the use of small nuclear power plants (SNPPs) at existing TPPs as heat sources for heat supply to municipal heating networks, there is a technological need to improve heat supply schemes to increase their environmental friendliness and efficiency. The paper proves the feasibility of using the heat-feeding mode of ASHPs for urban heat supply by heating the network water with steam taken from the turbine. The ratio of electric and thermal power of a “nuclear” combined heat and power plant is given. The advantage of using a heat pump, which provides twice as much electrical power with the same heat output, is established. Taking into account that heat in these modes is supplied with different potential, the energy efficiency was used to compare these options. To increase the heat supply capacity, a scheme with the use of a high-pressure heater in the backpressure mode and with the heating of network water with hot steam was proposed. Heat supply from ASHPs is efficient and environmentally friendly even in the case of significant remoteness of heat consumers.

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.

Low Power Polarity Conversion Based on the Whole Annealing Genetic Algorithm

For an n-variable logic function,the power dissipation and area of the REED-MULLER （RM） circuit corresponding to each polarity are different. Based on the propagation algorithm of signal probability,the decomposition algorithm of a multi-input XOR/AND gate,and the multiple segment algorithm of polarity conversion,this paper successfully applies the whole annealing genetic algorithm （WAGA） to find the best polarity of an RM circuit. Through testing eight large-scale circuits from the Microelectronics Center North Carolina （MCNC） Benchmark, the SYNOPSYS synthesis results show that the RM circuits corresponding to the best polarity found using the proposed algorithm attain average power,area,and max delay savings of 77.2% ,62.4% ,and 9.2% respectively,compared with those under polarity 0.

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

An ultra-low-power,256-bit EEPROM is designed and implemented in a Chartered 0.35μm EEPROM process. The read state power consumption is optimized using a new sense amplifier structure and an optimized control circuit. Block programming/erasing is achieved using an improved control circuit. An on silicon program/erase/read access time measurement design is given. For a power supply voltage of 1.8V,an average power consumption of 68 and 0.6μA for the program/erase and read operations,respectively,can be achieved at 640kHz.

Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies

Two new circuit techniques to suppress leakage currents and enhance noise immunity while decreasing the active power are proposed. Eight-input OR gate circuits constructed with these techniques are simulated using 45nm BSIM4 SPICE models in HSPICE. The simulation results show that the proposed circuits effectively lower the active power, reduce the total leakage current, and enhance speed under similar noise immunity conditions. The active power of the two proposed circuits can be reduced by up to 8. 8% and 11.8% while enhancing the speed by 9.5% and 13.7% as compared to dual Vt domino OR gates with no gating stage. At the same time,the total leakage currents are also reduced by up to 80.8% and 82.4% ,respectively. Based on the simulation results,the state of the evaluation node is also discussed to reduce the total leakage currents of dual Vt dominos.

Low Power Design Orienting 384×288 Snapshot Infrared Readout Integrated Circuits

This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share buffered direct injection （QSBDI） is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance, and low power usage. This ROIC also supports two integration modes （integration then readout and integration while readout）, two selectable gains, and four window readout modes. A test 128 × 128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only lmW,and the total power dissipation is 37mW at a working frequency of 4MHz.

Implementation and noise optimization of a 433 MHz low power CMOS LNA

A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.

Low-Power CMOS IC for Function Electrical Stimulation of Nerves

A low-power IC for function electrical stimulation （FES） of nerves is designed for an implantable system and fabricated in CSMC＇s 0.6μm CMOS technology. The IC can be used for stimulating animals＇ spinal nerve bundles and other nerves connected with a cuff type electrode. It consists of a pre-amplifier,a main amplifier,and an output stage. According to the neural signal spectrum,the bandwidth of the FES signal generator circuit is defined from 1Hz to 400kHz. The gain of the circuit is about 66dB with an output impedance of 900. The 1C can function under a single supply voltage of 3-5V. A rail-to-rail output stage helps to use the coupled power efficiently. The measured time domain performance shows that the bandwidth and the gain of the IC agree with the design. The power consumption is lower than 6mW.

A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors

A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

A 1.45GHz LNA with Low Power,Wide Variable Gain Range and Ultra Low Noise Degradation

A LNA with a novel variable gain solution is presented.Compared with the conventional variable gain solutions of LNA,which have more noise degradations when in low gain mode,this solution gives about 25dB variable gain range in 3dB steps,which would cause ultra low noise figure degradation by 0 3～0 5dB.In addition,extra power consumption is not needed by this solution compared with other solutions.

High Performance VHF Power VDMOSFETs for Low Voltage Applications

A high performance VHF power VDMOSFET,ap plying to the mobile communications,is developed,which can deliver an output power of 12W with the drain efficiency of 70% as well as the gain of 12dB at a low supply voltage of 12V and 175MHz.It is fabricated by using the terraced gat e structure and refractory molybdenum (Mo) gate technology.

A Low-Voltage,Low-Power CMOS High Dynamic Range dB-Linear VGA for Super Heterodyne Receivers

This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.

A Low-Voltage,High Efficiency Power Generation Structure for UHF RFID

This paper presents a new power generation structure that can provide DC energy for passive UHF RFID with high sensitivity and high efficiency. The structure is designed with 0.18μm standard CMOS technology, including two charge pumps,a current reference, and a group of bias circuits. Low-voltage performance is improved thanks to the bias structure,which eliminates the threshold voltage drop and body-effect of conventional circuits. A 350mV minimum input level is required to generate a 1.5V power supply for a 100k~ load with power conversion efficiency （PCE） of 22%. PCE up to 29.8% is achieved with a 60kΩ load. Simulation results show that the new circuit is superior to conventional charge pumps.

A Low Voltage,Low Power RF/Analog Front-End Circuit for Passive UHF RFID Tags

This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference generator using sub-threshold techniques. The chip maintains a steady system clock in a temperature range from - 40 to 100℃. Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator. The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0. 18μm CMOS EEPROM technology without Schottcky diodes. Measured results show that the chip has a minimum supply voltage requirement of 0.75V. At this voltage, the total current consumption of the RF/analog frontend circuit is 4.6μA.

Nested Miller Active-Capacitor Frequency Compensation for Low-Power Three-Stage Amplifiers

A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.

A Low-Power,Single-Poly,Non-Volatile Memory for Passive RFID Tags

Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.

20 Gbit/s 1∶2 demultiplexer of low-power using 0.18 μm CMOS

A 1 ： 2 demultiplexer（DEMUX） that is fabricated using 0. 18 μm CMOS （complementary metaloxide-semiconductor transistor） technology is presented. The DEMUX consists of a master-slave-slave, masterslave D flip-flops and output buffers. The D flip-flop employs a dynamic-loading structure and common-gate topology with single clock phase for the bias transistors. The dynamic-loading structure can make the circuit work faster because it decreases the charge/discharge time of the output node, and it consumes lower power because its working current is in a switch mode. In addition, the positive feedback loop, which is made up of a cross-coupled transistor pair in the latch, speeds up the circuit. Measurement results at 20 Gbit/s 2^23 - 1 pseudo random bit sequence （PRBS） via on-wafer testing show that the 1： 2 DEMUX can operate well. The power dissipation is 108 mW with the area of 475μm×578μm.

Self-Aligned InGaP/GaAs Power HBTswith a Low Bias Voltage

A self aligned InGaP/GaAs power HBTs for L band power amplifier with low bias voltage are described.Base emitter metal self aligning,air bridge,and wafer thinning are used to improve microwave power performance.A power HBT with double size of emitter of (3μm×15μm)×12 is fabricated.When the packaged HBT operates in class AB at a collector bias of 3V,a maximum 23dBm output power with 45% power added efficiency is achieved at 2GHz.The results show that the InGaP/GaAs power HBTs have great potential in mobile communication systems operating at low bias voltage.

A 0.18μm Transmitter and Receiver with High Speed and Low Power

This paper describes the design of a low voltage differential signal （LVDS） transmitter and receiver with high speed and low power for CPU, LCD, FPGA, and other fast links. In the proposed transmitter, a stable reference and a common mode feedback circuit are integrated into the LVDS drivers, which enable the transmitter to tolerate variations of process, temperature, and supply voltage. The proposed receiver implements a rail-to-rail amplifier architecture that allows a 1.6Gb/s transmission. The transmitter and receiver are implemented in HJ TC 3.3V,0. 18μm CMOS technology. The experimental results demonstrate that the transmitter and receiver reach 1.6Gb/s. The transmitter and receiver pad cells exhibit a power consumption of 35 and 6mW,respectively.

Design of CMOS class-E power amplifier for low power applications

A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.