High Performance VHF Power VDMOSFETs for Low Voltage Applications

A high performance VHF power VDMOSFET,ap plying to the mobile communications,is developed,which can deliver an output power of 12W with the drain efficiency of 70% as well as the gain of 12dB at a low supply voltage of 12V and 175MHz.It is fabricated by using the terraced gat e structure and refractory molybdenum (Mo) gate technology.

A Low-Voltage,Low-Power CMOS High Dynamic Range dB-Linear VGA for Super Heterodyne Receivers

This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC＇s 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements.

A Low-Voltage,High Efficiency Power Generation Structure for UHF RFID

This paper presents a new power generation structure that can provide DC energy for passive UHF RFID with high sensitivity and high efficiency. The structure is designed with 0.18μm standard CMOS technology, including two charge pumps,a current reference, and a group of bias circuits. Low-voltage performance is improved thanks to the bias structure,which eliminates the threshold voltage drop and body-effect of conventional circuits. A 350mV minimum input level is required to generate a 1.5V power supply for a 100k~ load with power conversion efficiency （PCE） of 22%. PCE up to 29.8% is achieved with a 60kΩ load. Simulation results show that the new circuit is superior to conventional charge pumps.

A Low Voltage,Low Power RF/Analog Front-End Circuit for Passive UHF RFID Tags

This paper presents a low voltage, low power RF/analog front-end circuit for passive ultra high frequency （UHF） radio frequency identification （RFID） tags. Temperature compensation is achieved by a reference generator using sub-threshold techniques. The chip maintains a steady system clock in a temperature range from - 40 to 100℃. Some novel building blocks are developed to save system power consumption,including a zero static current power-on reset circuit and a voltage regulator. The RF/analog front-end circuit is implemented with digital base-band and EEPROM to construct a whole tag chip in 0. 18μm CMOS EEPROM technology without Schottcky diodes. Measured results show that the chip has a minimum supply voltage requirement of 0.75V. At this voltage, the total current consumption of the RF/analog frontend circuit is 4.6μA.

Self-Aligned InGaP/GaAs Power HBTswith a Low Bias Voltage

A self aligned InGaP/GaAs power HBTs for L band power amplifier with low bias voltage are described.Base emitter metal self aligning,air bridge,and wafer thinning are used to improve microwave power performance.A power HBT with double size of emitter of (3μm×15μm)×12 is fabricated.When the packaged HBT operates in class AB at a collector bias of 3V,a maximum 23dBm output power with 45% power added efficiency is achieved at 2GHz.The results show that the InGaP/GaAs power HBTs have great potential in mobile communication systems operating at low bias voltage.

Analysis and management strategies for the low voltage problems of rural power grid based on the distribution network flow calculation method

For a long time, because of the lack of investment capital and enough attentions, the overall constructions of rural power grid were far behind than the urban power grid in Chongqing Jiangbei Power Company. The low voltage problems were highlighted in the rural power grid due to the characteristics of rural power grid. Using the distribution network flow calculation method, we evaluated the low voltage problems of the rural power grid which belongs to Chongqing Jiangbei Power Company. In addition, we collected the data of distribution transformers in electricity consumption peak period. Some practical management strategies were proposed by the analysis and evaluation of potential and appeared low voltage problems.

Very Low Power,Low Voltage,High Accuracy,and High Performance Current Mirror

A novel low power and low voltage current mirror with a very low current copy error is presented and the principle of its operation is discussed. In this circuit, the gain boosting regulated cascode scheme is used to improve the output resistance, while using inverter as an amplifier. The simulation results with HSPICE in TSMC 0.18 μm CMOS technology are given, which verify the high performance of the proposed structure. Simulation results show an input resistance of 0.014 Ω and an output resistance of 3 GΩ. The current copy error is favorable as low as 0.002% together with an input （the minimum input voltage of Vin,min- 0.24 V） and an output （the minimum output voltage of Vout,min~ 0.16 V） compliances while working with the 1 V power supply and the 50 μA input current. The current copy error is near zero at the input current of 27 μA. It consumes only 76μW and introduces a very low output offset current of 50 pA.

Improved RF power performance of InAlN/GaN HEMT by optimizing rapid thermal annealing process for high-performance low-voltage terminal applications

Improved radio-frequency(RF)power performance of InAlN/GaN high electron mobility transistor(HEMT)is achieved by optimizing the rapid thermal annealing(RTA)process for high-performance low-voltage terminal applications.By optimizing the RTA temperature and time,the optimal annealing condition is found to enable low parasitic resistance and thus a high-performance device.Besides,compared with the non-optimized RTA HEMT,the optimized one demonstrates smoother ohmic metal surface morphology and better heterojunction quality including the less degraded heterojunction sheet resistance and clearer heterojunction interfaces as well as negligible material out-diffusion from the barrier to the channel and buffer.Benefiting from the lowered parasitic resistance,improved maximum output current density of 2279 mA·mm^(-1)and higher peak extrinsic transconductance of 526 mS·mm^(-1)are obtained for the optimized RTA HEMT.In addition,due to the superior heterojunction quality,the optimized HEMT shows reduced off-state leakage current of 7×10^(-3)mA·mm^(-1)and suppressed current collapse of only 4%,compared with those of 1×10^(-1)mA·mm^(-1)and 15%for the non-optimized one.At 8 GHz and V_(DS)of 6 V,a significantly improved power-added efficiency of 62%and output power density of 0.71 W·mm^(-1)are achieved for the optimized HEMT,as the result of the improvement in output current,knee voltage,off-state leakage current,and current collapse,which reveals the tremendous advantage of the optimized RTA HEMT in high-performance low-voltage terminal applications.

Reactive Current Allocation and Control Strategies Improvement of Low Voltage Ride Though for Doubly Fed Induction Wind Turbine Generation System

为满足风电机组低电压穿越（low voltage ride through,LVRT）的测试要求及其电气模型一致性评估需要,提出考虑向电网注入无功电流的双馈风电机组LVRT的控制策略。在阐述风电机组LVRT测试要求及控制原理的基础上,推导双馈发电机（doubly fed induction generator,DFIG）定子侧及网侧变流器输出无功电流极限表达式,研究电网电压跌落深度和发电机总输出有功功率对其无功电流极限值的影响规律,进而提出DFIG在LVRT期间的无功电流分配算法和改进的有功、无功功率控制策略。最后,以某实际2 MW双馈风电机组为例,分别对风速为5和12 m/s、电网电压对称跌落至20%和50%工况下的LVRT运行性能进行仿真比较和样机测试。与传统LVRT控制方法的对比表明,所提改进控制策略能更好地满足风电机组LVRT的测试要求。样机测试结果进一步证明了改进控制策略和仿真模型的有效性。

Implementation strategy for soft switching PFC with low output voltage

This paper proposes a novel implementation strategy for soft switching PFC whose circuit is simple and can achieve low voltage output directly. The main circuit adopts current mode full-bridge converter and all the power switches can realize ZCS or ZVS in the way of phase-shlfted control, using the leakage inductance of the transformer, the junction capacitor of the switches and the stored energy of the output capacitor. The problems such as the function of phase-shlfted link in control circuit, the implementation conditions of soft switching and bias restrained are analyzed. The adoption of constant frequency PWM control makes the design of the input and output filter link and the high frequency transformer simple. The transformation ratio regulation so as to achieve low voltage output and electrical insulation can be realized by using high frequency transformer.

Low Voltage Ride through Control Capability of a Large Grid Connected PV System Combining DC Chopper and Current Limiting Techniques

This paper presents the development and performance capability of a comprehensive Low voltage ride through (LVRT) control scheme that makes use of both the DC chopper and the current limiting based on the required reactive power during fault time. The study is conducted on an 8.5 MW single stage PV power plant (PVPP) connected to the Rwandan grid. In the event of fault disturbance, this control scheme helps to overcome the problems of excessive DC-link voltage by fast activation of the DC chopper operation. At the same instance, AC current is limited to the maximum rating of the inverter as a function of the injected reactive current. This helps overcome AC-over- current that may possibly lead to damage or disconnection of the inverter. The control scheme also ensures voltage support and power balance through the injection of reactive current as per grid code requirements. Selected simulations using MATLAB are carried out in the events of different kinds of fault caused voltage dips. Results demonstrate the effectiveness of the proposed LVRT control scheme.

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.

A Novel Ultra Low Power High Performance Atto-Ampere CMOS Current Mirror with Enhanced Bandwidth

A novel CMOS atto-ampere current mirror （AACM） is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed circuit has a simple structure prohibiting large chip area consumption which consumes extremely low power of 1.5 μW. It is thus the best choice for ultra low power low voltage （ULPLV） applications. By using a very simple frequency compensation technique, its bandwidth is widened to 15.8 kHz. Simulation results in SMIC （Semiconductor Manufacturing International Corporation） 0.18 μm CMOS technology with Hspice are presented to demonstrate the validation of the proposed current mirror.

Low power and high speed explicit-pulsed double-edge triggered level converting flip-flop

Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.

Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application

This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 - 6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than –10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over –10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is –7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.

Ultra-Low Power, Low Phase Noise 10 GHz LC VCO in the Subthreshold Regime

A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is -107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is -193.8 dB, which this result shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.

A 5mW 1.8V Low Over-Sampling Ratio ΣΔ Modulator with 81dB Dynamic Range

This work demonstrates that the ΣΔ modulator with a low oversampling ratio is a viable option for the high-resolution digitization in a low-voltage environment.Low power dissipation is achieved by designing a low-OSR modulator based on differential cascade architecture,while large signal swing maintained to achieve a high dynamic range in the low-voltage environment.Operating from a voltage supply of 1.8V,the sixth-order cascade modulator at a sampling frequency of 4-MHz with an OSR of 24 achieves a dynamic range of 81dB for a 80-kHz test signal,while dissipating only 5mW.

RTLPower:一个实时动态电压调节低功耗系统

功耗问题是计算机系统发展亟待解决的问题,硬件和软件在解决功耗问题上都有重要的作用。尽管有许多工具可用于低功耗硬件的开发,但支持软件技术开发的低功耗工具并不多见。我们基于ARM的指令集开发了一个实时动态电压调节低功耗系统RTLPower。RTLPower综合了编译指导的动态电压调节和程序的性能功耗模拟,该系统能够有效支持编译指导的动态电压调节技术的研究开发。

Analysis and Design of a Low-Cost RFID Tag Analog Front-End

A new,low-cost RFID tag analog front-end compatible with ISO 14443A and ISO 14443B is presented. By substituting conventional multi-circle antenna with single-circle antenna, the package cost of the tag is greatly reduced. Based on this exasperate antenna performance,a new rectifier with high power conversion efficiency and low turn-on voltage is presented. The circuit is implemented in an SMIC 0.18μm EEPROM process. Measurement results show that with a 120kΩ load,the power conversion efficiency reaches as high as 36%. For a sinusoidal wave with magnitude of 0. 5V, the output DC voltage reaches IV,which is high enough for RFID tags. The read distance is as far as 22cm.

考虑LVRT特性的新能源送端系统功角稳定与电压稳定交互影响分析

新能源机组的低电压穿越(LVRT)能力是高比例新能源电力系统维持电压稳定的重要保证,同时LVRT期间新能源机组的功率特性将进一步影响同步发电机的功角稳定性。为分析高比例新能源送端系统功角稳定与电压稳定的耦合机理,以风电为例,推导了LVRT期间风电机组的有功-无功耦合关系;以含风电的送端系统为例,推导了故障前、故障期间以及故障后同步发电机的机械功率和电磁功率。分析了受扰后系统功角与电压的失稳形态,揭示了含风电送端系统功角稳定和电压稳定的交互影响。基于PSASP平台,仿真分析了风电初始出力水平以及LVRT参数对电力系统功角稳定和电压稳定演化的影响。