REGULAR LOW-DENSITY PARITY-CHECK CODES BASED ON SHIFTED IDENTITY MATRICES

This paper extends the class of Low-Density Parity-Check (LDPC) codes that can be constructed from shifted identity matrices. To construct regular LDPC codes, a new method is proposed. Two simple inequations are adopted to avoid the short cycles in Tanner graph, which makes the girth of Tanner graphs at least 8. Because their parity-check matrices are made up of circulant matrices, the new codes are quasi-cyclic codes. They perform well with iterative decoding.

CONSTRUCTION OF NONSYSTEMATIC LOW-DENSITY PARITY-CHECK CODES BASED ON SYMMETRIC BALANCED INCOMPLETE BLOCK DESIGN

This paper studies the nonsystematic Low-Density Parity-Check(LDPC)codes based onSymmetric Balanced Incomplete Block Design(SBIBD).First,it is concluded that the performancedegradation of nonsystematic linear block codes is bounded by the average row weight of generalizedinverses of their generator matrices and code rate.Then a class of nonsystematic LDPC codes con-structed based on SBIBD is presented.Their characteristics include:both generator matrices andparity-check matrices are sparse and cyclic,which are simple to encode and decode;and almost arbi-trary rate codes can be easily constructed,so they are rate-compatible codes.Because there aresparse generalized inverses of generator matrices,the performance of the proposed codes is only0.15dB away from that of the traditional systematic LDPC codes.

Low-Complexity Optimization Algorithm for Irregular Low-Density Parity-Check Codes

A low-complexity algorithm is proposed in this paper in order to optimize irregular low-density parity-check （LDPC） codes.The algorithm proposed can calculate the noise threshold by means of a one-dimensional density evolution and search the optimal degree profiles with fast-convergence differential evolution,so that it has a lower complexity and a faster convergence speed.Simulation resuits show that the irregular LDPC codes optimized by the presented algorithm can also perform better than Turbo codes at moderate block length even with less computation cost.

Implementation of low-density parity-check codes decoder for CCSDS standard

The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space Data Systems （CCSDS） standard is achieved in DSP. An ap- proximate decoding algorithm, normalized rain-sum algorithm, is used in the implementation for its low amounts of computation. To reduce the performance loss caused by the approximation, the pa- rameters of the normalized min-sum algorithm are determined by calculating and finding the mini- mum value of thresholds through density evolution. The minimum value which indicates the best per- formance of the decoding algorithm is corresponding with the optimized parameters. In implementa- tion, the memory cost is saved by decomposing the parity-check matrix into submatrices to store and the computation of passing message in decoding is accelerated by using the intrinsic function of DSP. The performance of the decoder with optimized factors is simulated and compared with the ideal BP decoder. The result shows they have about the same performance.

THE Q-MATRIX LOW-DENSITY PARITY-CHECK CODES

This paper presents a matrix permuting approach to the construction of Low-Density Parity-Check (LDPC) code. It investigates the structure of the sparse parity-check matrix defined by Gallager. It is discovered that the problem of constructing the sparse parity-check matrix requires an algorithm that is efficient in search environments and also is able to work with constraint satisfaction problem. The definition of Q-matrix is given, and it is found that the queen algorithm enables to search the Q-matrix. With properly permuting Q-matrix as sub-matrix, the sparse parity-check matrix which satisfied constraint condition is created, and the good regular-LDPC code that is called the Q-matrix LDPC code is generated. The result of this paper is significant not only for designing low complexity encoder, improving performance and reducing complexity of iterative decoding arithmetic, but also for building practical system of encodable and decodable LDPC code.

Low-Density Parity-Check Codes: Research Status and Development Direction

In this paper, we conclude five kinds of methods for construction of the regular low-density parity matrix H and three kinds of methods for the construction of irregular low-density parity-check matrix H. Through the analysis of the code rate and parameters of these eight kinds of structures, we find that the construction of low-density parity-check matrix tends to be more flexible and the parameter variability is enhanced. We propose that the current development cost should be lower with the progress of electronic technology and we need research on more practical Low-Density Parity-Check Codes (LDPC). Combined with the application of the quantum distribution key, we urgently need to explore the research direction of relevant theories and technologies of LDPC codes in other fields of quantum information in the future.

DESIGN OF LOW-DENSITY PARITY CHECK CODES FOR MIMO SYSTEMS WITH DOUBLY-ITERATIVE RECEIVERS

In this paper, the Multiple Input Multiple Output (MIMO) doubly-iterative receiver which consists of the Probabilistic Data Association detector (PDA) and Low-Density Parity-Check Code (LDPC) decoder is developed. The receiver performs two iterative decoding loops. In the outer loop, the soft information is exchanged between the PDA detector and the LDPC decoder. In the inner loop, it is exchanged between variable node and check node decoders inside the LDPC decoder. On the light of the Extrinsic Information Transfer (EXIT) chart technique, an LDPC code degree profile optimization algorithm is developed for the doubly-iterative receiver. Simulation results show the doubly-receiver with optimized irregular LDPC code can have a better performance than the one with the regular one.

Efficient construction and encoding of QC-LDPC codes by cyclic lifting of protographs

Quasi-cyclic low-density parity-check （QC-LDPC） codes can be constructed conveniently by cyclic lifting of protographs. For the purpose of eliminating short cycles in the Tanner graph to guarantee performance, first an algorithm to enumerate the harmful short cycles in the protograph is designed, and then a greedy algorithm is proposed to assign proper permutation shifts to the circulant permutation submatrices in the parity check matrix after lifting. Compared with the existing deterministic edge swapping （DES） algorithms, the proposed greedy algorithm adds more constraints in the assignment of permutation shifts to improve performance. Simulation results verify that it outperforms DES in reducing short cycles. In addition, it is proved that the parity check matrices of the cyclic lifted QC-LDPC codes can be transformed into block lower triangular ones when the lifting factor is a power of 2. Utilizing this property, the QC- LDPC codes can be encoded by preprocessing the base matrices, which reduces the encoding complexity to a large extent.

Implementation of encoder and decoder for LDPC codes based on FPGA

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.

Erasure-Correction-Enhanced Iterative Decoding for LDPC-RS Product Codes

Low-density parity-check(LDPC)codes are widely used due to their significant errorcorrection capability and linear decoding complexity.However,it is not sufficient for LDPC codes to satisfy the ultra low bit error rate(BER)requirement of next-generation ultra-high-speed communications due to the error floor phenomenon.According to the residual error characteristics of LDPC codes,we consider using the high rate Reed-Solomon(RS)codes as the outer codes to construct LDPC-RS product codes to eliminate the error floor and propose the hybrid error-erasure-correction decoding algorithm for the outer code to exploit erasure-correction capability effectively.Furthermore,the overall performance of product codes is improved using iteration between outer and inner codes.Simulation results validate that BER of the product code with the proposed hybrid algorithm is lower than that of the product code with no erasure correction.Compared with other product codes using LDPC codes,the proposed LDPC-RS product code with the same code rate has much better performance and smaller rate loss attributed to the maximum distance separable(MDS)property and significant erasure-correction capability of RS codes.

Weighted symbol-flipping decoding algorithm for nonbinary LDPC codes with flipping patterns

A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.

Design of good QC-LDPC codes without small girth in the p-plane

A construction method based on the p-plane to design high-girth quasi-cyclic low-density parity-check （QC-LDPC） codes is proposed. Firstly the good points in every line of the p-plane can be ascertained through filtering the bad points, because the designed parity-check matrixes using these points have the short cycles in Tanner graph of codes. Then one of the best points from the residual good points of every line in the p-plane will be found, respectively. The optimal point is also singled out according to the bit error rate （BER） performance of the QC-LDPC codes at last. Explicit necessary and sufficient conditions for the QC-LDPC codes to have no short cycles are presented which are in favor of removing the bad points in the p-plane. Since preventing the short cycles also prevents the small stopping sets, the proposed construction method also leads to QC-LDPC codes with a higher stopping distance.

DESIGN OF QUASI-CYCLIC LDPC CODES BASED ON EUCLIDEAN GEOMETRIES

A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and the designed codes perform very close to the Shannon limit with iterative decoding. Simulations show that the designed QC-LDPC codes have almost the same performance with the existing EG-LDPC codes.

PERFORMANCE OF SIMPLE-ENCODING IRREGULAR LDPC CODES BASED ON SPARSE GENERATOR MATRIX

A new method for the construction of the high performance systematic irregular low-density paritycheck （LDPC） codes based on the sparse generator matrix （G-LDPC） is introduced. The code can greatly reduce the encoding complexity while maintaining the same decoding complexity as traditional regular LDPC （H-LDPC） codes defined by the sparse parity check matrix. Simulation results show that the performance of the proposed irregular LDPC codes can offer significant gains over traditional LDPC codes in low SNRs with a few decoding iterations over an additive white Gaussian noise （AWGN） channel.

Analysis of LDPC Code in Hybrid Communication Systems

Free-space optical(FSO)communication is of supreme importance for designing next-generation networks.Over the past decades,the radio frequency(RF)spectrum has been the main topic of interest for wireless technology.The RF spectrum is becoming denser and more employed,making its availability tough for additional channels.Optical communication,exploited for messages or indications in historical times,is now becoming famous and useful in combination with error-correcting codes(ECC)to mitigate the effects of fading caused by atmospheric turbulence.A free-space communication system(FSCS)in which the hybrid technology is based on FSO and RF.FSCS is a capable solution to overcome the downsides of current schemes and enhance the overall link reliability and availability.The proposed FSCS with regular low-density parity-check(LDPC)for coding techniques is deliberated and evaluated in terms of signal-to-noise ratio(SNR)in this paper.The extrinsic information transfer(EXIT)methodology is an incredible technique employed to investigate the sum-product decoding algorithm of LDPC codes and optimize the EXIT chart by applying curve fitting.In this research work,we also analyze the behavior of the EXIT chart of regular/irregular LDPC for the FSCS.We also investigate the error performance of LDPC code for the proposed FSCS.

Irregular and regular LDPC codes with high spectrum efficiency modulation in image transmission over fading channel

If the degree distribution is chosen carefully, the irregular low-density parity-check (LDPC) codes can outperform the regular ones. An image transmission system is proposed by combining regular and irregular LDPC codes with 16QAM/64QAM modulation to improve both efficiency and reliability. Simulaton results show that LDPC codes are good coding schemes over fading channel in image communication with lower system complexity. More over, irregular codes can obtain a code gain of about 0.7 dB compared with regular ones when BER is 10 -4. So the irregular LDPC codes are more suitable for image transmission than the regular codes.

Ensemble of High Performance Structured Binary Convolutional LDPC Codes with Moderate Rates

An algebraic construction methodology is proposed to design binary time-invariant convolutional low-density parity-check(LDPC)codes.Assisted by a proposed partial search algorithm,the polynomialform parity-check matrix of the time-invariant convolutional LDPC code is derived by combining some special codewords of an(n,2,n−1)code.The achieved convolutional LDPC codes possess the characteristics of comparatively large girth and given syndrome former memory.The objective of our design is to enable the time-invariant convolutional LDPC codes the advantages of excellent error performance and fast encoding.In particular,the error performance of the proposed convolutional LDPC code with small constraint length is superior to most existing convolutional LDPC codes.

Construction of Regular Rate-Compatible LDPC Convolutional Codes

In this paper, we propose a new method to derive a family of regular rate-compatible low-density parity-check（RC-LDPC） convolutional codes from RC-LDPC block codes. In the RC-LDPC convolutional family, each extended sub-matrix of each extended code is obtained by choosing specified elements from two fixed matrices HE1K and HE1K, which are derived by modifying the extended matrices HE1 and HE2 of a systematic RC-LDPC block code. The proposed method which is based on graph extension simplifies the design, and prevent the defects caused by the puncturing method. It can be used to generate both regular and irregular RC-LDPC convolutional codes. All resulted codes in the family are systematic which simplify the encoder structure and have maximum encoding memories which ensure the property. Simulation results show the family collectively offer a steady improvement in performance with code compatibility over binary-input additive white Gaussian noise channel（BI-AWGNC）.

JOINT SOURCE-CHANNEL DECODING OF HUFFMAN CODES WITH LDPC CODES

In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).

QUASI-SYSTEMATIC BLOCK-CIRCULANT LDPC CODES

A class of Quasi-Systematic Block-Circulant Low-Density Parity-Check(QSBC-LDPC) codes is proposed.Block-circulant LDPC codes have been studied a lot recently,because the simple structures of their parity-check matrices are very helpful to reduce the implementation complexities.QSBC-LDPC codes are special block-circulant LDPC codes with quasi-systematic parity-check ma-trices.The memories for encoders of QSBC-LDPC codes are limited,and the encoding process can be carried out in a simple recursive way with low complexities.Researches show that the QSBC-LDPC codes can provide remarkable performances with low encoding complexities.