An NMOS output-capacitorless low-dropout regulator with dynamic-strength event-driven charge pump

In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.

A Capacitor-Free CMOS Low-Dropout Regulator for System-on-Chip Application

A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor. The chip was implemented in CSMC＇s 0.5μm CMOS technology and the die area is 600μm×480μm. The error of the output voltage due to line variation is less than -＋ 0.21% ,and the quiescent current is 39.8μA. The power supply rejection ratio at 100kHz is -33.9dB, and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV √Hz, respectively.

CMOS low-dropout regulator with 3.3 μA quiescent current without off-chip capacitor

A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.

Analysis and Design of a High-Stability,High-Accuracy,Low-Dropout Voltage Regulator

A high-accuracy,low-dropout （LDO） voltage regulator is presented. Using the slow-rolloff frequency compensation scheme, the LDO effectively overcomes the stability problem, facilitates the use of a ceramic capacitor, and improves the output voltage accuracy, which is critical for powering high-performance analog circuitry. The slow-rolloff compensation scheme is realized by introducing three pole-zero pairs, including the proposed polezero pair and sense zero. The post-layout simulation results demonstrate that this LDO has robust system stability, a high open-loop gain, and a high unit-gain frequency,which lead to excellent regulation and transient response performance. The line and load regulation are 27μV/V and 3.78μV/mA, and the overshoots of the output voltage are less than 30mV,while the dropout voltage is 120mV for a 150mA load current.

An Ultra-Low Quiescent Current CMOS Low-Dropout Regulator with Small Output Voltage Variations

An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.

Dose-rate effects of low-dropout voltage regulator at various biases

A low-dropout voltage regulator,LM2941,was irradiated by ^(60)Coγ-rays at various dose rates and biases for investigating the total dose and dose rate effects.The radiation responses show that the key electrical parameters, including its output and dropout voltage,and the maximum output current,are sensitive to total dose and dose rates, and are significantly degraded at low dose rate and zero bias.The integrated circuits damage change with the dose rates and biases,and the dose-rate effects are relative to its electric field.

Dual Micro-power 150mA Ultra LDO CMOS Regulator with Fast Startup

This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMOS Process.It can guarantee 150mA output current per circuit and the leakage voltage is 60mV,1nA quiescent current when both are in shutdown mode,and it has 115μA ground current,output noise is 42μVrms,130μs fast turn-on circuitry and the junction temperature range is-40℃to 125℃.

一种低功耗高稳定性的LDO设计

基于Nuvoton 0.35μm CMOS工艺,设计了一种低功耗、高稳定性、高瞬态响应的无片外电容低压差线性稳压器(LDO)。误差放大器为交叉耦合结构,通过调节耦合对的比例可在低电流下获得相对大带宽和高增益,从而保证系统稳定性。电路基于自适应偏置结构,动态跟随负载电流变化,为前级误差放大器提供偏置电流,提高环路带宽进而提高LDO的瞬态响应。仿真结果表明,LDO的输入范围为1.3~3.3 V,输出电压稳定在1.2 V,压差仅为100 mV;全负载范围内相位裕度(PM)最差为64.4°;负载电流在0.1μA~20 mA跳变时,欠冲电压为71.52 mV、恢复时间为526 ns,过冲电压为90.217 mV、恢复时间为568 ns,最小静态电流为5.17μA。

A comparative study of digital low dropout regulators

Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.

一种高PSR低静态电流LDO设计

设计了一种基于0.18μm BCD工艺的高电源抑制(PSR)低静态电流低压差线性稳压器(LDO)。详细分析了多条电源噪声传递路径对系统PSR的影响。为优化系统中低频段PSR,设计了一种双轨供电的三级误差放大器。此外还引入了预稳压单元,降低了电压基准模块对系统低频段PSR的影响。为降低系统的静态电流,设计了一种基于耗尽管的超低静态电流电压基准。仿真结果表明,该LDO在不同输出电压下静态电流仅5μA,并且在250 mA负载电流内PSR<-110 dB@1 kHz, PSR<-55 dB@1 MHz。

一种用于低噪声LDO的动态零点补偿技术

为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出电压经反馈网络传递给反馈端的信号耦合形成由负载电容、负载电流控制的可控零点,可有效提高LDO电路整体的稳定性。此外,电路内部加入了产生动态极点的自适应电流补偿电路以保证次极点不会对环路的相位裕度产生影响。基于0.18μm BCD工艺设计,该电路在0~800 mA的宽负载范围、5 V输入3.3 V输出下相位裕度均高于48°,适用负载电容范围≥1μF,同时该LDO在10~100 kHz的频率范围内输出噪声仅为5.0617μVrms。

无电容型LDO的研究现状与进展

无电容型低压差线性稳压器(LDO)除具有低噪声和高精度的特点外,还具有便于SoC系统集成和低应用成本的优点。与传统LDO相比,无电容型LDO无法利用输出电容的ESR补偿零点,也无法使输出电容在负载电流瞬态变化时为其提供充放电电流,从而在稳定性和瞬态特性上遇到巨大挑战。分析讨论了无电容型LDO的设计挑战;回顾了无电容型LDO在提高稳定性和改善瞬态特性上的最新研究成果。

利用动态密勒补偿电路解决LDO的稳定性问题

针对LDO稳压器的稳定性问题,设计了一种新颖的动态密勒补偿电路。与传统方法相比,该电路具有恒定的带宽,大大提高了系统的瞬态响应性能;同时将开环增益提高了30 dB左右,使LDO稳压器具有较高的电压调整率和负载调整率。通过具体投片,验证了该方法的正确性和可行性。

一种快速瞬态响应双环路LDO稳压器的设计

通过对传统单环LDO的频域分析,提出一种快速瞬态响应的双环路LDO稳压器结构,在保证单位增益带宽不变的前提下提高直流增益,进而提高LDO电路的瞬态性能。设计采用0.6μm BiCMOS高压工艺,Hspice仿真中输出电容为2.2μF,ESR为0.5Ω,旁路电容为1.0μF。负载电流从20 mA到180 mA变化时,其负载调整率仅为0.6%。

LDO线性稳压器中高性能误差放大器的设计

设计了一个共源共栅运算跨导放大器,并成功地将其应用在一款超低功耗LDO线性稳压器芯片中。该设计提高了电源抑制比(PSRR),并具有较高的共模抑制比(CMRR)。电路结构简单,静态电流低。该芯片获得了高达99 dB的电源抑制比。

一种新型双极型LDO线性稳压器的设计

L DO线性稳压器的低漏失电压、低静态电流特性使电池使用具有高效率和长寿命。针对这 2个主要特性和使能开关、过温过流保护等功能 ,本文设计并实现了一种新型的双极型 L DO线性稳压器 ,调整管采用自由集电极纵向 PNP管。

基于全反馈的高稳定性LDO线性稳压器

提出了一种新型结构的高稳定性LDO线性稳压器。该电路采用基于轨至轨误差放大器的全反馈模式;设计了包括转换速率加强(SRE)电路的缓冲电路,并采用跨多级双密勒电容补偿方式。在Chartered 0.35μm CMOS工艺下进行仿真,结果表明:输出电压跟踪基准电压变化范围为GND～Vdd;在0～300 mA的电流负载下,开环电路相位裕度均不小于88°;负载电流从0 mA跳变到50 mA时,输出电压最大跳变值和环路响应时间分别为28 mV和0.5μs。用全反馈网络替代LDO的电阻反馈网络,提高了输出电压精度,减小了系统静态电流、噪声和面积。

一种新颖的LDO线性稳压器

设计了一种新颖的LDO线性稳压器。该LDO工作于负电源,具有微功耗、自身固定-5V输出、外接反馈电阻可实现可调输出等特点。基于0.6μm SOI CMOS工艺进行流片。测试结果表明,该电路输入电源电压VIN为-2～-18V,可调输出电压为-1.3V～VIN+0.5V@IOUT=15mA。该LDO功耗低,室温下空载静态电流约4.8μA,并且几乎不随VIN变化。内部带隙电压基准采用β二阶补偿,结构简单,温度系数为1.28×10-5/℃。线性调整率为0.015%,负载调整率为0.85Ω。

LDO调制的电荷泵稳压电路设计

随着SOC技术的兴起和发展,便携式电子设备对电源管理芯片的需求大、要求高,要求提供稳定低噪的电压外,还要求低功耗和高转化效率。采用LDO电路结合电荷泵电路形成闭环反馈的稳压电路,利用电容电压不能突变的思想,在反馈状态下实现升降压的稳压电路。完成了LDO电路原理分析、稳压电路设计、带隙基准电路设计、误差放大器电路设计并进行了仿真验证,仿真结果表明,输入电压在2.7～5.5V之间时,输出稳定为5V。采用LDO调制的电荷泵稳压电路设计的电源管理芯片,能广泛应用在便携式电子产品当中。

一种新颖的BiC MOS高精度LDO线性稳压电路

设计了一种改进结构的用于锂离子和锂聚合物电池充电管理芯片的高精度、宽电源电压范围LDO线性稳压电路,电路采用0.8μm N阱BiCMOS高压工艺制作。Hspice仿真结果表明,在温度从-20℃到100℃变化时,其温度系数约为±28 ppm/℃;电源电压从4.5 V到25 V变化时,最坏情况下其线性调整率为0.038 mV/V;负载电流从0到满载2 mA变化时,其负载调整率仅为1.28 mV/mA。