A survey of FPGA design for AI era

FPGA is an appealing platform to accelerate DNN.We survey a range of FPGA chip designs for AI.For DSP module,one type of design is to support low-precision operation,such as 9-bit or 4-bit multiplication.The other type of design of DSP is to support floating point multiply-accumulates(MACs),which guarantee high-accuracy of DNN.For ALM(adaptive logic module)module,one type of design is to support low-precision MACs,three modifications of ALM includes extra carry chain,or 4-bit adder,or shadow multipliers which increase the density of on-chip MAC operation.The other enhancement of ALM or CLB(configurable logic block)is to support BNN(binarized neural network)which is ultra-reduced precision version of DNN.For memory modules which can store weights and activations of DNN,three types of memory are proposed which are embedded memory,in-package HBM(high bandwidth memory)and off-chip memory interfaces,such as DDR4/5.Other designs are new architecture and specialized AI engine.Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform.Its AI engine can provide up to 8X silicon compute density.Intel AgileX in 10 nm works coherently with Intel own CPU,which increase computation performance,reduced overhead and latency.

Automatic Terrain Debris Recognition Network Based on 3D Remote Sensing Data

Although predecessors have made great contributions to the semantic segmentation of 3D indoor scenes,there still exist some challenges in the debris recognition of terrain data.Compared with hundreds of thousands of indoor point clouds,the amount of terrain point cloud is up to millions.Apart from that,terrain point cloud data obtained from remote sensing is measured in meters,but the indoor scene is measured in centimeters.In this case,the terrain debris obtained from remote sensing mapping only have dozens of points,which means that sufficient training information cannot be obtained only through the convolution of points.In this paper,we build multi-attribute descriptors containing geometric information and color information to better describe the information in low-precision terrain debris.Therefore,our process is aimed at the multi-attribute descriptors of each point rather than the point.On this basis,an unsupervised classification algorithm is proposed to divide the point cloud into several terrain areas,and regard each area as a graph vertex named super point to form the graph structure,thus effectively reducing the number of the terrain point cloud from millions to hundreds.Then we proposed a graph convolution network by employing PointNet for graph embedding and recurrent gated graph convolutional network for classification.Our experiments show that the terrain point cloud can reduce the amount of data from millions to hundreds through the super point graph based on multi-attribute descriptor and our accuracy reached 91.74%and the IoU reached 94.08%,both of which were significantly better than the current methods such as SEGCloud(Acc:88.63%,IoU:89.29%)and PointCNN(Acc:86.35,IoU:87.26).

Analysis and Research on Low-Cost and Non-Intrusive Power Metering Chip

Metering technology is one of the core technologies of the smart power grid. The overall metering solution and related products have a wide market space in the whole process of power production, which bring new opportunities for power distribution development from automation to intelligentialize, and provide technical supports for the power metering system platform. Because of the importance of metering products and their market demand, this paper focuses on the design of a simple power metering chip with low-cost, low-precision and non-invasive, so as to lay the foundation for the development and practical technology accumulation of power metering products. The design achieves low cost by reducing the acquisition accuracy, simplifying the collection and sampling methods. This paper studies the chip accuracy, sampling methods, collection methods, and the inference of the chip characteristics requirements.