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High-Voltage MOSFETs in a 0.5μm CMOS Process
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作者 赵文彬 李蕾蕾 于宗光 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第7期1268-1273,共6页
There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commerci... There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices. 展开更多
关键词 high-voltage mOSFET low-voltage mOSFET 0.5μm cmos process embedded manufacture technology
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一种2μmp阱CMOS工艺 被引量:1
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作者 蒋志 王勇 华光平 《微电子学》 CAS CSCD 1994年第2期51-55,共5页
本文介绍了我们开发的2μmp阱CMOS工艺,包括不同工艺方案的设计,主要参数的选取、调整及实验结果。给出不同工艺方案的比较及实验结果对比,最后给出我们选定的2μmp阱CMOS工艺方案及主要电学参数。
关键词 2微米工艺 cmos技术 工艺 集成电路
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2μmp阱CMOS工艺中提高源-漏穿通电压的方法 被引量:1
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作者 蒋志 王勇 赵海军 《微电子学》 CAS CSCD 1994年第3期31-33,共3页
采用防穿通注入的工艺方案,对提高2μmpMOS管的源漏穿通电压应选用的工艺条件做了实验研究。给出了加防穿通注入工艺的实验结果及其对V_(Tp)的影响。
关键词 cmos 工艺 源漏穿通电压 mp阱
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A Quadrature Oscillator Based on a New “Optimized DDCC” All-Pass Filter
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作者 Achwek Ben Saied Samir Ben Salem Dorra Sellami Masmoudi 《Circuits and Systems》 2013年第8期498-503,共6页
In this paper, a new voltage-mode (VM), all-pass filter utilizing two second-generation current conveyors and tow differential difference current conveyors (DDCCs) is proposed. This filter uses a number of passive ele... In this paper, a new voltage-mode (VM), all-pass filter utilizing two second-generation current conveyors and tow differential difference current conveyors (DDCCs) is proposed. This filter uses a number of passive elements grounded capacitor. This structure of filter is used to realize a quadrature oscillator. The proposed circuits employ tow optimized differential difference translinear second generation current conveyers (DDCCII). These structures are simulated using the spice simulation in the ADS software and CMOS 0.18 μm process of TSMC technology to confirm the theory. The pole frequency can be tuned in the range of [11.6 - 39.6 MHz] by a simple variation of a DC current. 展开更多
关键词 Proposed CURRENT CONTROLLED Oscillators cmos 0.18 μm process of TSmC CURRENT CONVEYOR DIFFERENTIAL DIFFERENCE CURRENT Conveyors
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