A low-power 14-bit 150MS/s analog-to-digital converter(ADC) is presented for communication applications.Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted.Opamp and capacitor sharing betwee...A low-power 14-bit 150MS/s analog-to-digital converter(ADC) is presented for communication applications.Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted.Opamp and capacitor sharing between the first multiplying digital-to-analog converter(MDAC)and the second one reduces the total opamp power further.The dedicated sample-andhold amplifier(SHA) is removed to lower the power and the noise.The blind calibration of linearity errors is proposed to improve the performance.The prototype ADC is fabricated in a 130 nm CMOS process with a 1.3-V supply voltage.The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input.It consumes 85 mW,which includes 57 mW for the ADC core,11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
The volume and exposure time of nuclear radiation detectors are different in the Marine environment.This paper selects γ-rays emitted by ^(131)I,^(137)Cs and ^(208)Tl radionuclides,and uses NaI detectors of different...The volume and exposure time of nuclear radiation detectors are different in the Marine environment.This paper selects γ-rays emitted by ^(131)I,^(137)Cs and ^(208)Tl radionuclides,and uses NaI detectors of different volumes to simulate the minimum detectable activity concentration(MDAC)at different exposure time.And this paper studies the relationship between the increase multiple of crystal volume and the decrease multiple of MDAC.In this paper,based on MDAC,the existence of nuclides at different crystal volumes and different exposure times was qualitatively calculated and analyzed,which will be of guiding significance to the in situ γ spectrum measurement and long-term monitoring of seawater.展开更多
A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk p...A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.展开更多
A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POT...A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.展开更多
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s analog-to-digital converter(ADC) is presented for communication applications.Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted.Opamp and capacitor sharing between the first multiplying digital-to-analog converter(MDAC)and the second one reduces the total opamp power further.The dedicated sample-andhold amplifier(SHA) is removed to lower the power and the noise.The blind calibration of linearity errors is proposed to improve the performance.The prototype ADC is fabricated in a 130 nm CMOS process with a 1.3-V supply voltage.The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input.It consumes 85 mW,which includes 57 mW for the ADC core,11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
基金National Defense Fundamental Research Project,JCKY2020404C004,Jiangmei ZhangNatural Science Foundation of Sichuan Province,22NSFSC2458,Jiangmei Zhang。
文摘The volume and exposure time of nuclear radiation detectors are different in the Marine environment.This paper selects γ-rays emitted by ^(131)I,^(137)Cs and ^(208)Tl radionuclides,and uses NaI detectors of different volumes to simulate the minimum detectable activity concentration(MDAC)at different exposure time.And this paper studies the relationship between the increase multiple of crystal volume and the decrease multiple of MDAC.In this paper,based on MDAC,the existence of nuclides at different crystal volumes and different exposure times was qualitatively calculated and analyzed,which will be of guiding significance to the in situ γ spectrum measurement and long-term monitoring of seawater.
基金Project supported by the National Natural Science Foundation of China(No.60876019)the National S&T Major Project of China(No. 2009ZX0131-002-003-02)+2 种基金the Shanghai Rising-Star Program(No.09QA1400300)the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046)the ASIC State-Key Laboratory Funding,China(No.09MS007)
文摘A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.
基金supported by the National Natural Science Foundation of China(Nos.61234002,61006028)the National High-Tech Program of China(Nos.2012AA012302,2013AA014103)the PhDProgram Foundation of Ministry of Education of China(No.20120203110017)
文摘A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.
