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Design of an Electrically Written and Optically Read Non-volatile Memory Device Employing BiFeO3/Au Heterostructures with Strong Absorption Resonance
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作者 肖鹏博 张伟 +2 位作者 曲天良 黄云 胡绍民 《Chinese Physics Letters》 SCIE CAS CSCD 2015年第7期67-70,共4页
Exploiting new concepts for dense, fast, and nonvolatile random access memory with reduced energy consump- tion is a significant issue for information technology. Here we design an 'electrically written and optically... Exploiting new concepts for dense, fast, and nonvolatile random access memory with reduced energy consump- tion is a significant issue for information technology. Here we design an 'electrically written and optically read' information storage device employing BiFeO3/A u heterostruetures with strong absorption resonance. The electro- optic effect is the basis for the device design, which arises from the strong absorption resonance in BiFeO3/Au heterostructures and the electrically tunable significant birefringence of the BiFeO3 film. We first construct a sim- ulation calculation of the BiFeO3/Au structure spectrum and identify absorption resonance and electro-optical modulation characteristics. Following a micro scale partition, the surface reflected light intensity of different polarization units is calculated. The results depend on electric polarization states of the BiFeO3 film, thus BiFeO3/Au heterostructures can essentially be designed as a type of electrically written and optically read infor- mation storage device by utilizing the scanning near-field optical microscopy technology based on the conductive silicon cantilever tip with nanofabricated aperture. This work will shed light on information storage technology. 展开更多
关键词 BFO design of an Electrically Written and Optically Read Non-volatile memory Device Employing BiFeO3/Au Heterostructures with Strong Absorption Resonance
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A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver
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作者 YU Shuangming FENG Peng WU Nanjian 《China Communications》 SCIE CSCD 2016年第1期33-46,共14页
The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power... The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation. 展开更多
关键词 LR-WPAN wake-up identification receiver synchronization non-volatile memory baseband processor digital integrated circuit low power chip design
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