THE KAKEYA MAXIMAL OPERATOR WITH A SPECIAL BASE to the memory of Professor Ruilin Long

Let M f be the Kakeya maximal function in d-dimensional Euclidean space, with same base consisting of cylinders of eccentricity N. The inequality shoum for a base satisfying a direction condition, where ?and c are constants depending only on d.

Three-Dimensional Simulations of RESET Operation in Phase-Change Random Access Memory with Blade-Type Like Phase Change Layer by Finite Element Modeling

An optimized device structure for reducing the RESET current of phase-change random access memory （PCRAM） with blade-type like （BTL） phase change layer is proposed. The electrical thermal analysis of the BTL cell and the blade heater contactor structure by three-dimensional finite element modeling are compared with each other during RESET operation. The simulation results show that the programming region of the phase change layer in the BTL cell is much smaller, and thermal electrical distributions of the BTL cell are more concentrated on the TiN/GST interface. The results indicate that the BTL cell has the superiorities of increasing the heating efficiency, decreasing the power consumption and reducing the RESET current from 0.67mA to 0.32mA. Therefore, the BTL cell will be appropriate for high performance PCRAM device with lower power consumption and lower RESET current.

Properties and Stability of Max-Product Fuzzy Bi-Directional Associative Memory

In this paper, a fuzzy operator of max-product is defined at first, and the fuzzy bi-directional associative memory (FBAM) based on the fuzzy operator of max-product is given. Then the properties and the Lyapunov stability of equilibriums of the networks are studied.

Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates

A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ~4 V, a small leakage current density of ~2 ×10-6 Acre-2 at a gate voltage of 7V, a high charge trapping density of 1.42 × 1013 cm-2 at a working vo]tage of 4-10 V and good retention characteristics are observed. Furthermore, the programming （△ VFB = 2.8 V at 10 V for 10μs） and erasing speeds （△VFB =-1.7 V at -10 V for 10μs） of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.