Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual...Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.展开更多
The effect of α phase on CuZnAl shape memo- ry alloy(SMA)has been systematically studied by electrical resistance method,quantitative measure- ment of micrography and transmission electron microscopy(TEM).It is found...The effect of α phase on CuZnAl shape memo- ry alloy(SMA)has been systematically studied by electrical resistance method,quantitative measure- ment of micrography and transmission electron microscopy(TEM).It is found that,by controlling the amount of α phase in(α+β)-CuZnAl alloy, phase transformation temperatures can be adjusted precisely in a wide range,while the good shape memory effect of CuZnAl is kept.In a word, quenching from(α+β)dual phase region is a rea- sonable method of adjusting phase transformation temperatures for CuZnAl alloy.展开更多
A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single po...A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single positive program voltage(VPP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time,securing the reliability of medium voltage(VM) devices that are thick gate transistors.A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop.For the newly proposed cell,a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse.The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 μm Bipolar-CMOS-DMOS(BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.展开更多
Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to acc...Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.展开更多
This paper proposes a new thermoviscoelastic finite deformation model incorporating dual relaxation mechanisms to predict the complete thermo-mechanical response of amorphous shape memory polymers.The model is underpi...This paper proposes a new thermoviscoelastic finite deformation model incorporating dual relaxation mechanisms to predict the complete thermo-mechanical response of amorphous shape memory polymers.The model is underpinned by the detailed microscopic molecular mechanism and effectively reflects the current understanding of the glass transition phenomenon.Novel evolution rules are obtained from the model to characterize the viscous flow,and a new theory named an internal stress model is introduced and combined with the dual relaxation mechanisms to capture the stress recovery.The rationality of the constitutive model is verified as the theoretical results agree well with the experimental data.Moreover,the constitutive model is further simplified to facilitate engineering applications,and it can roughly capture the characteristics of shape memory polymers.展开更多
In this paper, a filtering method is presented to estimate time-varying parameters of a missile dual control system with tail fins and reaction jets as control variables. In this method, the long-short-term memory(LST...In this paper, a filtering method is presented to estimate time-varying parameters of a missile dual control system with tail fins and reaction jets as control variables. In this method, the long-short-term memory(LSTM) neural network is nested into the extended Kalman filter(EKF) to modify the Kalman gain such that the filtering performance is improved in the presence of large model uncertainties. To avoid the unstable network output caused by the abrupt changes of system states,an adaptive correction factor is introduced to correct the network output online. In the process of training the network, a multi-gradient descent learning mode is proposed to better fit the internal state of the system, and a rolling training is used to implement an online prediction logic. Based on the Lyapunov second method, we discuss the stability of the system, the result shows that when the training error of neural network is sufficiently small, the system is asymptotically stable. With its application to the estimation of time-varying parameters of a missile dual control system, the LSTM-EKF shows better filtering performance than the EKF and adaptive EKF(AEKF) when there exist large uncertainties in the system model.展开更多
文摘Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed.This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory(DPCAM).In addition,it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm(NFRA)to reduce the cost overhead of the cache controller and improve the cache access latency.The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory.Moreover,it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM.However,an estimation of the power dissipation showed that DPCAM consumes about 7%greater than a set-associative cache memory of the same size.These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.
文摘The effect of α phase on CuZnAl shape memo- ry alloy(SMA)has been systematically studied by electrical resistance method,quantitative measure- ment of micrography and transmission electron microscopy(TEM).It is found that,by controlling the amount of α phase in(α+β)-CuZnAl alloy, phase transformation temperatures can be adjusted precisely in a wide range,while the good shape memory effect of CuZnAl is kept.In a word, quenching from(α+β)dual phase region is a rea- sonable method of adjusting phase transformation temperatures for CuZnAl alloy.
基金Work supported by the Second Stage of Brain Korea 21 Projectssupported by Changwon National University in 2009-2010
文摘A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single positive program voltage(VPP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time,securing the reliability of medium voltage(VM) devices that are thick gate transistors.A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield drop.For the newly proposed cell,a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the antifuse.The layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 μm Bipolar-CMOS-DMOS(BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.
文摘Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.
基金This work is supported by the National Natural Science Foundation of China(Grant No.:12202181)the Natural Science Foundation of Jiangsu Province of China(Grant No.:BK20220325)the Fund of Prospective Layout of Scientific Research for Nanjing University of Aeronautics and Astronautics.
文摘This paper proposes a new thermoviscoelastic finite deformation model incorporating dual relaxation mechanisms to predict the complete thermo-mechanical response of amorphous shape memory polymers.The model is underpinned by the detailed microscopic molecular mechanism and effectively reflects the current understanding of the glass transition phenomenon.Novel evolution rules are obtained from the model to characterize the viscous flow,and a new theory named an internal stress model is introduced and combined with the dual relaxation mechanisms to capture the stress recovery.The rationality of the constitutive model is verified as the theoretical results agree well with the experimental data.Moreover,the constitutive model is further simplified to facilitate engineering applications,and it can roughly capture the characteristics of shape memory polymers.
文摘In this paper, a filtering method is presented to estimate time-varying parameters of a missile dual control system with tail fins and reaction jets as control variables. In this method, the long-short-term memory(LSTM) neural network is nested into the extended Kalman filter(EKF) to modify the Kalman gain such that the filtering performance is improved in the presence of large model uncertainties. To avoid the unstable network output caused by the abrupt changes of system states,an adaptive correction factor is introduced to correct the network output online. In the process of training the network, a multi-gradient descent learning mode is proposed to better fit the internal state of the system, and a rolling training is used to implement an online prediction logic. Based on the Lyapunov second method, we discuss the stability of the system, the result shows that when the training error of neural network is sufficiently small, the system is asymptotically stable. With its application to the estimation of time-varying parameters of a missile dual control system, the LSTM-EKF shows better filtering performance than the EKF and adaptive EKF(AEKF) when there exist large uncertainties in the system model.
