Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors （MOSF- FETs） have been fabricated and characterized. A sandwich- （nitridation-oxidation-nitridation） type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.

Mobility enhancement of strained GaSb p-channel metal-oxide-semiconductor field-effect transistors with biaxial compressive strain

Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.

Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation

A power metal-oxide-semiconductor field-effect transistor(MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electric field at reversed blocking state has been studied. To analyze the electric field, the drift region is segmented into four regions, where the conformal mapping method based on Schwarz–Christoffel transformation has been applied. According to the analysis, the improvement in the electric field for using the low permittivity trench is mainly due to the two electric field peaks generated in the drift region around this dielectric trench. The analytical results of the electric field and the potential models are in good agreement with the simulation results.

Evaluation of a gate-first process for AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with low ohmic annealing temperature

In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors （MOS- HFETs） were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.

Influences of fringing capacitance on threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor

Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor（MOSFET） are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability （NBTI） has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors （MOSFETs）. The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^＋ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^＋ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^＋ generated during NBTI stress.

Effect of depositing PCBM on perovskite-based metal–oxide–semiconductor field effect transistors

In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and characterized by photoluminescence spectra（PL）,x-ray diffraction（XRD）,and x-ray photoelectron spectroscopy（XPS）.With PCBM layers,the current–voltage hysteresis phenomenon is effetely inhibited,and both the transfer and output current values increase.The band energy diagrams are proposed,which indicate that the electrons are transferred into the PCBM layer,resulting in the increase of photocurrent.The electron mobility and hole mobility are extracted from the transfer curves,which are about one order of magnitude as large as those of PCBM deposited,which is the reason why the electrons are transferred into the PCBM layer and the holes are still in the perovskites,and the effects of ionized impurity scattering on carrier transport become smaller.

Stacked lateral double-diffused metal–oxide–semiconductor field effect transistor with enhanced depletion effect by surface substrate

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.

Investigation of trap states in Al_2O_3 InAlN/GaN metal–oxide–semiconductor high-electron-mobility transistors

In this paper the trapping effects in Al2O3/In0.17Al0.83N/GaN MOS-HEMT（here, HEMT stands for high electron mobility transistor） are investigated by frequency-dependent capacitance and conductance analysis. The trap states are found at both the Al2O3/In AlN and InAlN/GaN interface. Trap states in InAlN/GaN heterostructure are determined to have mixed de-trapping mechanisms, emission, and tunneling. Part of the electrons captured in the trap states are likely to tunnel into the two-dimensional electron gas（2DEG） channel under serious band bending and stronger electric field peak caused by high Al content in the In AlN barrier, which explains the opposite voltage dependence of time constant and relation between the time constant and energy of the trap states.

Performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors （MOSHEMTs） and InA1N/GaN high electron mobility transistors （HEMTs）. The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device, while the gate leakage current in the reverse direction could be reduced by four orders of magnitude. Compared with the HEMT device of a similar geometry, MOSHEMT presents a large gate voltage swing and negligible current collapse.

New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor （4H-SiC MESFET） structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications. The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one- and two-dimensional Poisson＇s equations. In the models, we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted. The direct-current and the alternating- current performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 ~tm are calculated. The calculated results are in good agreement with the experimental data. The current is larger than that of the conventional structure. The cutoff frequency （fT） and the maximum oscillation frequency （fmax） are 20.4 GHz and 101.6 GHz, respectively, which are higher than 7.8 GHz and 45.3 GHz of the conventional structure. Therefore, the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.

Metal oxide ion gated transistors based sensors

Metal oxide ion-gated transistors(MOIGTs)have garnered significant attention within the sensing domain due to their potential for achieving heightened sensitivity while consuming minimal energy across diverse scenarios.By harnessing the advantageous combination of metal oxides'high carrier mobility and facile surface customization,coupled with the potent signal amplification capabilities of ion-gated transistors,MOIGTs offer a promising avenue for discerning biomolecules,overseeing chemical reactions,p H levels,as well as facilitating gas or light determination.Over the past few decades,the MOIGT field has made remarkable strides in refining device physics,enhancing material properties,showcasing robust sensing capabilities,and broadening its application spectrum.These advancements have simultaneously unveiled new challenges and opportunities,necessitating interdisciplinary expertise to fully unlock the commercial potential of MOIGTs.In this comprehensive review,we offer a snapshot of this swiftly evolving technology,delve into its current applications,and provide insightful recommendations for future directions in the coming decade.

X-ray irradiation-induced degradation in Hf_(0.5)Zr_(0.5)O_(2) fully depleted silicon-on-insulator n-type metal oxide semiconductor field-effect transistors

The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulator,were fabricated.The total ionizing dose effects were investigated,and an X-ray radiation dose up to 1500 krad(Si) was applied for both long-and short-channel devices.The short-channel devices(0.025-0.100 μm) exhibited less irradiation sensitivity compared with the long-channel devices(0.35-16 μm),leading to a 71% reduction in the irradiation-induced drain current growth and a 26% decrease in the shift of the threshold voltage.It was experimentally demonstrated that the OFF mode is the worst case among the three working conditions(OFF,ON and A110) for short-channel devices.Also,the determined effective electron mobility was enhanced by 38% after X-ray irradiation,attributed to the different compensations for charges triggered by radiation between the highk dielectric and buried oxide.By extracting the carrier mobility,gate length modulation,and source/drain(S/D)parasitic resistance,the degradation mechanism on X-ray irradiation was revealed.Finally,the split capacitance-voltage measurements were used to validate the analysis.

High-performance junction field-effect transistor based on black phosphorus/β-Ga2O3 heterostructure

Black phosphorous(BP),an excellent two-dimensional(2D)monoelemental layered p-type semiconductor material with high carrier mobility and thickness-dependent tunable direct bandgap structure,has been widely applied in various devices.As the essential building blocks for modern electronic and optoelectronic devices,high quality PN junctions based on semiconductors have attracted widespread attention.Herein,we report a junction field-effect transistor(JFET)by integrating narrow-gap p-type BP and ultra-wide gap n-typeβ-Ga2O3 nanoflakes for the first time.BP andβ-Ga2O3 form a vertical van der Waals(vdW)heterostructure by mechanically exfoliated method.The BP/β-Ga2O3 vdW heterostructure exhibits remarkable PN diode rectifying characteristics with a high rectifying ratio about 107 and a low reverse current around pA.More interestingly,by using the BP as the gate andβ-Ga2O3 as the channel,the BP/β-Ga2O3 JFET devices demonstrate excellent n-channel JFET characteristics with the on/off ratio as high as 107,gate leakage current around as low as pA,maximum transconductance(gm)up to 25.3μS and saturation drain current(IDSS)of 16.5μA/μm.Moreover,it has a pinch-off voltage of–20 V and a minimum subthreshold swing of 260 mV/dec.These excellent n-channel JFET characteristics will expand the application of BP in future nanoelectronic devices.

适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究

SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。

大功率射频Si-VDMOS功率晶体管研制

介绍了大功率射频硅-垂直双扩散金属氧化物场效应晶体管(Si-VDMOS)的研制结果,采用栅分离降低反馈电容技术、多子胞降低源极电感技术等,从芯片原理着手,比较分析两种芯片结构设计对反馈电容的影响,以及两种布局引线对源极电感的影响,并研制出了百瓦级以上大功率射频Si-VDMOS功率晶体管系列产品。产品主要性能如下:在工作电压28 V及连续波下,采用8胞合成时,225 MHz输出功率达200 W以上,500 MHz输出功率达150 W以上;进一步增加子胞数量,采用12胞合成时,225 MHz输出功率达300 W以上,同时具备良好的增益及效率特性,与国外大功率射频Si-VDMOS功率晶体管的产品参数相比,达到了同类产品水平。

SiC MOSFET开关瞬态解析建模综述

在评估和优化半导体器件开关瞬态特性领域,解析模型因具有简单、直观、应用便捷等优点得到广泛研究。相较同等功率等级的硅基功率器件,碳化硅(silicon carbide,SiC)金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)可以应用于更高开关速度,其开关瞬态特性更为复杂,开关瞬态解析建模也更加困难。该文总结现有的针对SiC MOSFET与二极管换流对的开关瞬态解析建模方法,在建模过程中依次引入各种简化假设,按照简化程度由低到高的顺序,梳理解析建模的逐步简化过程。通过对比,评估各模型的优缺点以及适用场合,对其中准确性、实用性都较强的分段线性模型进行详细介绍;之后,对开关瞬态建模中关键参数的建模方法进行总结与评价;最后,指出现有SiC MOSFET开关瞬态解析模型中存在的问题,并对其未来发展给出建议。

双沟槽SiC金属-氧化物-半导体型场效应管重离子单粒子效应

本文针对第四代双沟槽型碳化硅场效应晶体管升展了不同源漏偏置电压下208 MeV锗离子辐照实验,分析了器件产生单粒子效应的物理机制.实验结果表明,辐照过程中随着初始偏置电压的增大,器件漏极电流增长更明显;在偏置电压为400 V时,重离子注量达到9×10^(4)ion/cm^(2),器件发生单粒子烧毁,在偏置电压为500 V时,重离子注量达到3×10^(4)ion/cm^(2),器件发生单粒子烧毁,单粒子烧毁阈值电压在器件额定工作电压的34%(400 V)以下.对辐照后器件进行栅特性测试,辐照过程中偏置电压为100 V的器件泄漏电流无明显变化;200 V和300 V时,器件的栅极泄漏电流和漏极泄漏电流都增大.结合TCAD仿真模拟进一步分析器件单粒子效应微观机制,结果表明在低偏压下,泄漏电流增大是因为电场集中在栅氧化层的拐角处,导致了氧化层的损伤;在高偏压下,辐照过程中N-外延层和N+衬底交界处发生的电场强度增大,引起显著的碰撞电离,由碰撞电离产生的局域大电流密度导致晶格温度超过碳化硅的熔点,最终引起单粒子烧毁.

SiC MOSFET高温栅氧可靠性研究

碳化硅SiC(silicon carbide)具有优良的电学和热学特性,是一种前景广阔的宽禁带半导体材料。SiC材料制成的功率MOSFET(metal-oxide-semiconductor field-effect transistor)非常适合应用于大功率领域,而高温栅氧可靠性是大功率MOSFET最需要关注的特性之一。通过正压高温栅偏试验和负压高温栅偏试验对比了自研SiC MOSFET和国外同规格SiC MOSFET的高温栅氧可靠性。负压高温栅偏试验结果显示自研SiC MOSFET与国外SiC MOSFET的阈值电压偏移量基本相等,阈值电压偏移量百分比最大相差在4.52%左右。正压高温栅偏试验的结果显示自研SiC MOSFET的阈值电压偏移量较小,与国外SiC MOSFET相比,自研SiC MOSFET的阈值电压偏移量百分比最大相差11%。自研器件占优势的原因是在SiC/SiO2界面处引入了适量的氮元素,钝化界面缺陷的同时,减少了快界面态的产生,使总的界面态密度被降到最低。