New 4H silicon carbide metal semiconductor field-effect transistor with a buffer layer between the gate and the channel layer

A new 4H silicon carbide metal semiconductor field-effect transistor （4H-SiC MESFET） structure with a buffer layer between the gate and the channel layer is proposed in this paper for high power microwave applications. The physics-based analytical models for calculating the performance of the proposed device are obtained by solving one- and two-dimensional Poisson＇s equations. In the models, we take into account not only two regions under the gate but also a third high field region between the gate and the drain which is usually omitted. The direct-current and the alternating- current performances for the proposed 4H-SiC MESFET with a buffer layer of 0.2 ~tm are calculated. The calculated results are in good agreement with the experimental data. The current is larger than that of the conventional structure. The cutoff frequency （fT） and the maximum oscillation frequency （fmax） are 20.4 GHz and 101.6 GHz, respectively, which are higher than 7.8 GHz and 45.3 GHz of the conventional structure. Therefore, the proposed 4H-SiC MESFET structure has better power and microwave performances than the conventional structure.

Stacked lateral double-diffused metal–oxide–semiconductor field effect transistor with enhanced depletion effect by surface substrate

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.

Metal–Organic Framework-Based Sensors for Environmental Contaminant Sensing

Increasing demand for timely and accurate environmental pollution monitoring and control requires new sensing techniques with outstanding performance, i.e.,high sensitivity, high selectivity, and reliability. Metal–organic frameworks(MOFs), also known as porous coordination polymers, are a fascinating class of highly ordered crystalline coordination polymers formed by the coordination of metal ions/clusters and organic bridging linkers/ligands. Owing to their unique structures and properties,i.e., high surface area, tailorable pore size, high density of active sites, and high catalytic activity, various MOF-based sensing platforms have been reported for environmental contaminant detection including anions, heavy metal ions,organic compounds, and gases. In this review, recent progress in MOF-based environmental sensors is introduced with a focus on optical, electrochemical, and field-effect transistor sensors. The sensors have shown unique and promising performance in water and gas contaminant sensing. Moreover, by incorporation with other functional materials, MOF-based composites can greatly improve the sensor performance. The current limitations and future directions of MOF-based sensors are also discussed.

X-ray irradiation-induced degradation in Hf_(0.5)Zr_(0.5)O_(2) fully depleted silicon-on-insulator n-type metal oxide semiconductor field-effect transistors

The n-type ultrathin fully depleted silicon-on-insulator(FDSOI) metal-oxide-semiconductor field-effect transistors(MOSFETs),with a Hf_(0.5)Zr_(0.5)O_(2) high dielectric permittivity(high-k) dielectric as gate insulator,were fabricated.The total ionizing dose effects were investigated,and an X-ray radiation dose up to 1500 krad(Si) was applied for both long-and short-channel devices.The short-channel devices(0.025-0.100 μm) exhibited less irradiation sensitivity compared with the long-channel devices(0.35-16 μm),leading to a 71% reduction in the irradiation-induced drain current growth and a 26% decrease in the shift of the threshold voltage.It was experimentally demonstrated that the OFF mode is the worst case among the three working conditions(OFF,ON and A110) for short-channel devices.Also,the determined effective electron mobility was enhanced by 38% after X-ray irradiation,attributed to the different compensations for charges triggered by radiation between the highk dielectric and buried oxide.By extracting the carrier mobility,gate length modulation,and source/drain(S/D)parasitic resistance,the degradation mechanism on X-ray irradiation was revealed.Finally,the split capacitance-voltage measurements were used to validate the analysis.

Experiment and simulation on degradation and burnout mechanisms of SiC MOSFET under heavy ion irradiation

Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5×10^(6)ion·cm^(-2), the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.

Proton induced radiation effect of SiC MOSFET under different bias

Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors(SiC MOSFETs)induced by 20 MeV proton under drain bias(V_(D)=800 V,V_(G)=0 V),gate bias(V_(D)=0 V,V_(G)=10 V),turn-on bias(V_(D)=0.5 V,V_(G)=4 V)and static bias(V_(D)=0 V,V_(G)=0 V)are investigated.The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation.When the cumulative proton fluence reaches 2×10^(11)p·cm^(-2),the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left,and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious.In the deep level transient spectrum test,it is found that the defect energy level of SiC MOSFET is mainly the ON2(E_(c)-1.1 eV)defect center,and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most.By comparing the degradation of SiC MOSFET under proton cumulative irradiation,equivalent 1 MeV neutron irradiation and gamma irradiation,and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET,the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage.The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.

Reversible and controllable threshold voltage modulation for n-channel MoS2 and p-channel MoTe_(2 )field-effect transistors via multiple counter doping with ODTS/poly-L-lysine charge enhancers

Confronted by the inherent physical limitations in scaling down Si technology,transition metal dichalcogenides(TMDCs)as alternatives are being tremendously researched and paid attention to.However,mature counter doping technology for TMDCs is still elusive,and thus,a controllable and reversible charge enhancer is adopted for acceptor(or donor)-like doping via octadecyltrichlorosilane(ODTS)(or poly-L-lysine(PLL))treatment.Furthermore,multiple counter doping for TMDC field-effect transistors(FETs),combined with a threshold voltage(V;h)freezing scheme,renders the V_(th) modulation controllable,with negligible degradation and decent sustainability of FETs even after each treatment of a representative charge enhancer.In parallel,the counter doping mechanism is systematically investigated via photoluminescence spectroscopy,X-ray photoelectron spectroscopy,atomic force microscopy(AFM),surface energy characterization,and measurement of optoelectronic properties under illumination with light of various wavelengths.More impressively,complementary inverters,composed of type-converted molybdenum ditelluride(MoTe_(2)>FETs and hetero-TMDC FETs in enhancement mode,are demonstrated via respective ODTS/PLL treatments.Herein,driving backplane application for micro-light-emitting diode(p-LED)displays and physical validation of a corresponding counter doping scheme even for flexible polyethylene terephthalate(PET)substrates could be leveraged to relieve daunting challenges in the application of nanoscale Si-based three-dimensional(3D)stacked systems,with potential adoption of ultralow power and monolithic optical interconnection technology.

High-performance MoS_(2)/p^(+)-Si heterojunction field-effect transistors by interface modulation

Molybdenum disulfide(MoS_(2)),one of transition metal dichalcogenides,is a promising semiconductor material for electronic or optoelectronic devices due to its favorably electronic properties.However,in metal-oxide semiconductor field-effect transistor(MOSFET)structures using MoS_(2),electrical performances such as mobility and subthreshold swing are suppressed by the interface trap density between the channel and dielectric layers.Moreover,the electrical stability of such structures is compromised due to interface traps and that can be analyzed such as current hysteresis and transient characteristics.Here,we demonstrate MoS_(2) heterojunction field-effect transistors(HFET)by applying MoS_(2)/p^(+)-Si heterojunctions and achieve high performance characteristics,including a mobility of 636.19 cm^(2)/(V∙s),a subthreshold swing of 67.4 mV/dec,minimal hysteresis of 0.05 V,and minimized transient characteristics.However,the HFET devices with varying the channel length demonstrated degradation of electrical performance with increasing the overlap area of the channel and dielectric layers.These results regarding MoS_(2)/p^(+)-Si HFETs resulted in the structural optimization of high-performance electronic devices for practical applications.

Crypto primitive of MOCVD MoS_(2) transistors for highly secured physical unclonable functions

Physically unclonable crypto primitives have potential applications for anti-counterfeiting,identification,and authentication,which are clone proof and resistant to variously physical attack.Conventional physical unclonable function(PUF)based on Si complementary metal-oxide-semiconductor(CMOS)technologies greatly suffers from entropy loss and bit instability due to noise sensitivity.Here we grow atomically thick MoS2 thin film and fabricate field-effect transistors(FETs).The inherently physical randomness of MoS2 transistors from materials growth and device fabrication process makes it appropriate for the application of PUF device.We perform electrical characterizations of MoS2 FETs,collect the data from 448 devices,and generate PUF keys by splitting drain current at specific levels to evaluate the response performance.Proper selection of splitting threshold enables to generate binary,ternary,and double binary keys.The generated PUF keys exhibit good randomness and uniqueness,providing a possibility for harvesting highly secured PUF devices with two-dimensional materials.

Effect of the Si-doped In_(0.49)Ga_(0.51)P barrier layer on the device performance of In_(0.4)Ga_(0.6)As MOSFETs grown on semi-insulating GaAs substrates

In0.4Ga0.6As channel metal-oxide-semiconductor field-effect transistors （MOSFETs） with and without an Si-doped In0.49Ga0.51P barrier layer grown on semi-insulating GaAs substrates have been investigated for the first time. Compared with the In0.4Ga0.6As MOSFETs without an In0.49Ga0.51P barrier layer, In0.4Ga0.6As MOSFETs with an In0.49Ga0.51P barrier layer show higher drive current, higher transconductance, lower gate leakage current, lower subthreshold swing, and higher effective channel mobility. These In0.4Ga0.6As MOSFETs （gate length 2 μm） with an In0.49Ga0.51P barrier layer exhibit a high drive current of 117 mA/mm, a high transconductance of 71.9 mS/mm, and a maximum effective channel mobility of 1266 cm2/（V·s）.

Spin transport in epitaxial Fe3O4/GaAs lateral structured devices

Research in the spintronics community has been intensively stimulated by the proposal of the spin field-effect transistor(SFET),which has the potential for combining the data storage and process in a single device.Here we report the spin dependent transport on a Fe_(3)O_(4)/GaAs based lateral structured device.Parallel and antiparallel states of two Fe_(3)O_(4) electrodes are achieved.A clear MR loop shows the perfect butterfly shape at room temperature,of which the intensity decreases with the reducing current,showing the strong bias dependence.Understanding the spin-dependent transport properties in this architecture has strong implication in further development of the spintronic devices for room-temperature SFETs.

Abnormal oxidation in nickel silicide and nickel germanosilicide in sub-micro CMOS

After post-silicidation annealing at various temperatures for 30 min, abnormal oxidation and agglomeration in nickel silicide and nickel germanosilicide are investigated under different conditions of NiSi, with As-, In-, and Sb-doped Si substrates of nickel germanosilicide without any dopants. The NiSi thickness, dopant species, doping concentration, and silicide process conditions are dominant factors for abnormal oxidation and NiSi agglomeration. Larger dopants than Si, thinner NiSi thickness and SiGe suhstrates, and higher dopant concentrations promote abnormal oxidation and agglomeration.

Topological structures of transition metal dichalcogenides: A review on fabrication, effects, applications, and potential

Transition metal dichalcogenides(TMDs)have received tremendous attention owing to their potential for optoelectronic applications.Topological structures,such as wrinkles,folds,and scrolls,have been generated on TMDs,thereby exhibiting novel physical properties with improved optoelectronic performance,making them attractive prospects for both basic understanding and advanced applications in optoelectronics.In this review,the methods for fabricating wrinkles,folds,and scrolls on TMDs are outlined,including modification of the fabrication and transfer processes,and manipulation via auxiliary polymers.The effects on their physical and electronic properties are also discussed,with particular paid to the energy band structure,single-photon sources,second harmonic generation(SHG),and interlayer coupling.In comparison to pristine TMDs,these topologies exhibit great advantages in optoelectronic devices,such as field-effect transistors and photodetectors.Finally,existing challenges and opportunities of wrinkled,folded,and scrolled TMDs are outlined and an outlook is presented.