Effects of La_(0.8)Sr_ (0.2)Mn(Fe)O_(3-δ) Protective Coatings on SOFC Metallic Interconnects

SUS430 （16% - 17% （mass fraction） Cr） can be used as interconnects for solid oxide fuel cells （SOFCs） that operate at lower temperatures （ 〈 800 ℃ ）. However, oxidation of steel can occur readily at elevated temperatures leading to the formation of Cr2O3 and spinel （Fe3O4） and thus greatly degrades the performance of the fuel cell. The aim of this work was to reduce oxide growth, in particular, the Cr2O3 phase, through the application of La0.8Sr0.2MnO3-δ （LSM2O） and La0.8Sr0.2FeO3-δ（LSF20） coatings by atmospheric plasma spraying technology （APS）. Oxide growth was characterized by using X-ray diffraction （XRD）, scanning electron microscopy （SEM） with an energy dispersive X-ray （EDX） analyzer. During oxidation of fifty 20 h cycles at 800 ℃ in air, the samples with coatings remained very stable, whereas significant spallation and weight loss were observed for the uncoated steel. LSF20 presents apparently advantages in reducing oxidation growth, interface resistance and inhibition of diffusion of chromium. After exposure in air at 800 ℃ for 1000 h, the interfacial resistance of LSF20-coated alloy is lowered by more than 23 times to that of LSM20-coated layer.

Fabrication of Gd_(2)O_(3)-doped CeO_(2)thin films through DC reactive sputtering and their application in solid oxide fuel cells

Physical vapor deposition(PVD)can be used to produce high-quality Gd_(2)O_(3)-doped CeO2(GDC)films.Among various PVD methods,reactive sputtering provides unique benefits,such as high deposition rates and easy upscaling for industrial applications.GDC thin films were successfully fabricated through reactive sputtering using a Gd_(0.2)Ce_(0.8)(at%)metallic target,and their application in solid oxide fuel cells,such as buffer layers between yttria-stabilized zirconia(YSZ)/La0.6Sr0.4Co0.2Fe0.8O_(3−δ)and as sublayers in the steel/coating system,was evaluated.First,the direct current(DC)reactive-sputtering behavior of the GdCe metallic target was determined.Then,the GDC films were deposited on NiO-YSZ/YSZ half-cells to investigate the influence of oxygen flow rate on the quality of annealed GDC films.The results demonstrated that reactive sputtering can be used to prepare thin and dense GDC buffer layers without high-temperature sintering.Furthermore,the cells with a sputtered GDC buffer layer showed better electrochemical performance than those with a screen-printed GDC buffer layer.In addition,the insertion of a GDC sublayer between the SUS441 interconnects and the Mn-Co spinel coatings contributed to the reduction of the oxidation rate for SUS441 at operating temperatures,according to the area-specific resistance tests.

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article,the design,fabrication and characterization of silicon carbide(SiC)complementary-metal-oxide-semiconductor(CMOS)-based integrated circuits(ICs)are presented.A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS(NMOS)and P-channel MOS(PMOS)devices that are required for the CMOS circuit configuration.Based on the mainstream 6-inch SiC wafer processing technology,the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized.Fundamental gates,such as inverter and NAND gates,are fabricated and tested.The measurement results show that the inverter and NAND gates function well.The calculated low-to-high delay(low-to-high output transition)and high-to-low delay(high-to-low output transition)are 49.9 and 90 ns,respectively.

Development of spin-on-glass process for triple metal interconnects

Spin-on-glass （SOG）, an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide （SiO2） deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO2 and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.