Micro-power negative pressure wound technique reduces risk of incision infection following loop ileostomy closure

BACKGROUND Prophylactic loop ileostomy is an effective way to reduce the clinical severity of anastomotic leakage following radical resection of rectal cancer.Incisional surgical site infection(SSI)is a common complication after ileostomy closure.AIM To evaluate the efficacy and safety of the micro-power negative pressure wound technique(MPNPWT)in preventing incisional SSI.METHODS This was a prospective,randomized controlled clinical trial conducted at a single center.A total of 101 consecutive patients who underwent ileostomy closure after rectal cancer surgery with a prophylactic ileostomy were enrolled from January 2019 to December 2021.Patients were randomly allocated into an MPNPWT group and a control group.The MPNPWT group underwent intermittent suturing of the surgical incision with 2-0 Prolene and was covered with a micro-power negative pressure dressing.The surgical outcomes were compared between the MPNPWT(n=50)and control(n=51)groups.Risk factors for incisional SSI were identified using logistic regression.RESULTS There were no differences in baseline characteristics between the MPNPWT(n=50)and control groups(n=51).The incisional SSI rate was significantly higher in the control group than in the MPNPWT group(15.7%vs 2.0%,P=0.031).However,MPNPWT did not affect other surgical outcomes,including intra-abdominal complications,operative time,and blood loss.Postoperative hospital stay length and hospitalization costs did not differ significantly between the two groups(P=0.069 and 0.843,respectively).None of the patients experienced adverse effects of MPNPWT,including skin allergy,dermatitis,and pain.MPNPWT also helped heal the infected incision.Our study indicated that MPNPWT was an independent protective factor[odds ratio(OR)=0.005,P=0.025)]and diabetes was a risk factor(OR=26.575,P=0.029)for incisional SSI.CONCLUSION MPNPWT is an effective and safe way to prevent incisional SSI after loop ileostomy closure.

RESEARCH AND APPLICATION OF LF WAKE-UP TECHNOLOGY TO MICRO-POWER ACTIVE RFID

Tags of micro-power active RFID system are usually supllied by cells battery, the power consumption is a crucial factor. The currently applied operating mode is of timing wake-up. In this paper, presented the method of LF wake-up technology , discussed how to use it to solve the low-power problem of active RFID tag. Put forward the crucial electrocircuit and working program flow. Practices show that this solution is capable of solving the problem of low-power of active RFID.

Dual Micro-power 150mA Ultra LDO CMOS Regulator with Fast Startup

This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMOS Process.It can guarantee 150mA output current per circuit and the leakage voltage is 60mV,1nA quiescent current when both are in shutdown mode,and it has 115μA ground current,output noise is 42μVrms,130μs fast turn-on circuitry and the junction temperature range is-40℃to 125℃.

Converged Communication Technology and Application in Intelligent Dual-Interactive Power System

Acknowledgments Thanks for assistance and support, which is provided by State Grid Corporation of China and State Grid Communication Information ＆ Telecommunication Company, for the project in the process of research and development. Fibrlink Communications Co., Ltd will keep exerting itself to innovating, which aims for making more contribution of the smart grid on energy reduction and environment protection.

A micro-power LDO with piecewise voltage foldback current limit protection

To achieve a constant current limit,low power consumption and high driving capability,a micro-power LDO with a piecewise voltage-foldback current-limit circuit is presented.The current-limit threshold is dynamically adjusted to achieve a maximum driving capability and lower quiescent current of only 300 nA.To increase the loop stability of the proposed LDO,a high impedance transconductance buffer under a micro quiescent current is designed for splitting the pole that exists at the gate of the pass transistor to the dominant pole,and a zero is designed for the purpose of the second pole phase compensation.The proposed LDO is fabricated in a BiCMOS process. The measurement results show that the short-circuit current of the LDO is 190 mA,the constant limit current under a high drop-out voltage is 440 mA,and the maximum load current under a low drop-out voltage is up to 800 mA. In addition,the quiescent current of the LDO is only 7μA,the load regulation is about 0.56%on full scale,the line regulation is about 0.012%/V,the PSRR at 120 Hz is 58 dB and the drop-out voltage is only 70 mV when the load current is 250 mA.