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RSSI Enhanced Microkernel-Based LBS Design 被引量:1
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作者 Tingyan Xing Shang Zhang Fan Zhang 《Journal of Geographic Information System》 2014年第2期109-114,共6页
Geographical Information System (GIS) always plays an integral role in LBS systems. But it comes with technology problems, such as less flexible, low efficiency, no redundancy of existing geographic information of app... Geographical Information System (GIS) always plays an integral role in LBS systems. But it comes with technology problems, such as less flexible, low efficiency, no redundancy of existing geographic information of application configuration which has high entry cost. At same time, indoors positioning is attracting more and more attention from research domain where GPS-like systems do not work. By RSSI location fingerprint data that sampling from the actual WSN environment, this article analyzed RF signal propagation characteristics in indoor from the point of view of the indoor positioning, and analyzed some factors that may affect the positioning error, which provided a theoretical basis for the positioning algorithm design and positioning system deployment. The aim of this paper is also to present a lightweight, efficient and scalable microkernel plug-in geospatial information application system and its implementation method for GIS in LBS design and practice. In this paper a software model called Resource loading manager (RLM) is designed. Through the RLM efficient allocation of geographic information resources and security management could be achieved. 展开更多
关键词 RLM MICROKERNEL LBS GIS
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IPC Mechanisms in Satellite Real-Time Microkernel Operating System
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作者 刘晓冬 李莲治 +1 位作者 郭福顺 朱力群 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 1998年第4期72-75,共4页
One of the most important features of modem minor satellites is to realize autonomous moving. The perfomance of the satellite autonomous computer operating system acting as the control center is of utrnost importance.... One of the most important features of modem minor satellites is to realize autonomous moving. The perfomance of the satellite autonomous computer operating system acting as the control center is of utrnost importance. The recent trend in operating system development is adopting microkernel architecture that holds such advantages as microminiaturization, modularity, portability and extendibility. IPC is the key of microkernel design. Message-based IPC mechanism is generally used in existing microkernel Operating system. It is of consistency, safety and reliability.However, it can not provide efficient support for real-time applications in satellite systems and it only applies to loose coupling multi-processor architecture. In this paper, an improvement solution for existing message-based IPC is proposed at first to obtain real-time performance. Then a new IPC mechanism is designed. It particulary applies to shared memory tight coupling multi-processor architecture. 展开更多
关键词 SATELLITE MICROKERNEL REAL-TIME IPC MECHANISM MESSAGE
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Microkernel Development for Embedded Systems
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作者 Rodrigo Maximiano Antunes de Almeida Luis Henrique de Carvalho Ferreira Carlos Henrique Valério 《Journal of Software Engineering and Applications》 2013年第1期20-28,共9页
This paper presents the development of a microkernel with a device driver controller for embedded systems. The implementation was done in C language aiming low cost microcontrollers. The proposed system allowed to per... This paper presents the development of a microkernel with a device driver controller for embedded systems. The implementation was done in C language aiming low cost microcontrollers. The proposed system allowed to perform soft real-time activities while keeping the drivers and the application isolated by a secure layer. The callback system proved itself extremely simple to use while still maintaining the security of the system regarding the temporal constraints. 展开更多
关键词 Embedded Systems MICROKERNEL Device DRIVER CONTROLLER HARDWARE Devices CALLBACK
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Microkernel and Middle-Ware Based GIS Platform Design
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作者 Tingyan Xing Shang Zhang Fan Zhang 《Positioning》 2014年第2期53-58,共6页
By contrasting the traditional way in which GIS was completed that comes with less flexible, low efficiency, and lack redundancy which cause high entry cost, the fast development of microkernel plug-in technology prov... By contrasting the traditional way in which GIS was completed that comes with less flexible, low efficiency, and lack redundancy which cause high entry cost, the fast development of microkernel plug-in technology provides the lightweight, efficient and scalable solution to Geographical Information System (GIS). This paper is to reveal the potential of microkernel plug-in geospatial information processing technology in GIS design and practice, with the acceptance and usage of function model called Resource loading manager(RLM) for GIS applications, which provides a possible solution to overcome the GIS’s high cost issue. After the short review of microkernel plug-in technology, the possibility of GIS design with microkernel is analyzed. This paper also introduced the composition of the whole system and the design of GIS service platform based on middle-ware in detail. 展开更多
关键词 MICROKERNEL LBS MIDDLE RLM
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The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy
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作者 Philip Machanick 《Journal of Computer Science & Technology》 SCIE EI CSCD 2005年第5期586-595,共10页
This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in... This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM's energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time (RAMpage without context switches on misses) of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.393, an acceptable trade-off (penalty under 10%) for being able to switch easily to a lower-energy mode. 展开更多
关键词 low-power design main memory virtual memory cache memories microkernels
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