Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers ...Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.展开更多
Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vert...Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.展开更多
The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double...The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.展开更多
提出以电流信号表示逻辑值的新型低噪声触发器设计,用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。所提出的设计包括主从型边沿触发器和单闩锁单边沿触发器。单个锁存器的电流型边沿触发器设计是通过在...提出以电流信号表示逻辑值的新型低噪声触发器设计,用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。所提出的设计包括主从型边沿触发器和单闩锁单边沿触发器。单个锁存器的电流型边沿触发器设计是通过在有效时钟沿后产生的窄脉冲使锁存器瞬时导通完成一次取样求值。与主从型触发器相比,单闩锁结构的触发器具有结构简单、直流功耗低的特点。采用0.25μm CM O S工艺参数的HSP ICE模拟结果表明,所提出的电流型触发器工作时,在电源端产生的电流波动远远小于传统的CM O S电路。展开更多
文摘Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.
基金Supported by the National Natural Science Foundation of China (Nos.60833004 and 60876026)the 3-D Floorplanning and Placement Project of the Intel Corporation
文摘Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.
文摘The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.
文摘提出以电流信号表示逻辑值的新型低噪声触发器设计,用于高性能混合集成电路的设计中以减少存贮单元开关噪声对模拟电路性能的影响。所提出的设计包括主从型边沿触发器和单闩锁单边沿触发器。单个锁存器的电流型边沿触发器设计是通过在有效时钟沿后产生的窄脉冲使锁存器瞬时导通完成一次取样求值。与主从型触发器相比,单闩锁结构的触发器具有结构简单、直流功耗低的特点。采用0.25μm CM O S工艺参数的HSP ICE模拟结果表明,所提出的电流型触发器工作时,在电源端产生的电流波动远远小于传统的CM O S电路。
