CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.

Sliding-mode Observer-based Grid Voltage-observation Method with Frequency-fixed Dual SOGI and Cross-compensated Phase-locked Loop

Conventional sliding-mode observer(SMO)-based grid-voltage observation methods often require a low-pass filter(LPF)to remove high-frequency sliding-mode noise.However,a complicated phase-and amplitude-compensation method,which is highly sensitive to the DC-offset,is required.A frequency-adaptive dual second-order generalized integrator(SOGI)can be used to replace the LPF,eliminating the compensation link and the effects of the DC-offset;however,strong coupling is introduced between the front-end SOGI block and back-end phase-locked loop(PLL)block,thereby reducing the dynamic performance.To solve this problem,this study proposes an SMO-based grid-voltage observation method with a frequency-fixed dual SOGI and cross-compensated PLL that can eliminate the frequency coupling between the front-end SOGI block and back-end PLL blocks,thereby increasing its dynamic performance.In this study,the phase and amplitude are compensated simultaneously using the proposed cross-compensation method,achieving an accurate observation of the grid voltage under off-nominal frequencies.An analysis of the small-signal model theoretically verified that the proposed method has good dynamic performance.Finally,the superiority of the proposed method is verified through comparative experiments.

Design and implementation of digital closed-loop drive control system of a MEMS gyroscope

In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.

Small-signal Stability Analysis and Improvement with Phase-shift Phase-locked Loop Based on Back Electromotive Force Observer for VSC-HVDC in Weak Grids

Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.

Ring-VCO-based phase-locked loops for clock generation–design considerations and state-of-the-art

This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.

Tracking error analysis and simulation of FLL-assisted PLL

In order to solve problems in high dynamic environment, a frequency-locked loop （FLL） assisted phase-locked loop （PLL） is put forward for carrier tracking. On the basis of the analysis of discriminators, the total phase error of the tracking loop is analyzed and a general error expression is derived. By using linearization and Jaffe-Rechtin coefficients, the performance of a special first order FLL-assisted second order PLL is analyzed to get a closed expression. Analysis results and simula- tions show that there exist an optimal FLL loop bandwidth and a optimal PLL loop bandwidth which can make the phase jitter much less than that when the PLL is used alone.

Low spurious noise frequency synthesis based on a DDS-driven wideband PLL architecture

An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer （ DDS ） -driven wideband phase-locked loop （PLL） architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor （DAC） output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range （SFDR） is about 64 dBc in a 320 MHz bandwidth.

Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m-C loop filter

This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in a phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore, the MASH 1-1-1 sigma-delta （ZA） modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and built-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 CHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.

Comparative Study of Single-phase Phase-locked Loops for Grid-connected Inverters Under Non-ideal Grid Conditions

In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.

DDS的杂散分析及频率扩展研究

介绍了在直接数字频率合成器 (DDS)成功开发的基础上扩展其频率上限的一些方法 ,同时对其杂散进行了分析。DDS芯片采用 AD985 2 ,控制电路采用 TMS32 0 C31,该数字频率合成器通过编程可方便地完成调幅、调频和调相功能 。

2.488 Gbit/s clock and data recovery circuit in 0.35 μm CMOS

The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.

一种超宽带超低相位噪声频率综合器

为了解决直接频率合成方法频带拓展困难和锁相频率合成方法相位噪声附加恶化严重的问题,设计了一种联合直接模拟频率合成和锁相频率合成的混频锁相频率综合器.该频率综合器采用梳谱发生器激励超低相位噪声的偏移信号后,再将该信号插入锁相环进行环内混频,降低鉴相器的倍频次数进而优化输出信号的相位噪声,同时解决了超宽带混频锁相环的错锁问题.该文设计的频率覆盖范围为12~24 GHz、步进为100 MHz的超宽带频率综合器实验测试表明:频率综合器在低频段12 GHz处相位噪声优于-116 dBc/Hz@1 kHz,在高频段24 GHz处相位噪声优于-109 dBc/Hz@1 kHz,相位噪声指标与直接模拟频率合成方法相当,均优于传统锁相方法20 dB以上.本文混合频率合成方法具有超宽带和超低相位噪声的优点,可以用于高性能的电子设备和系统.

一种简单可靠的高速宽带混频环防错锁方案及工程设计

对混频环设计中的关键技术问题混频环的捕捉带、高速防错锁电路的设计进行了研究,推导出了基本混频环捕捉带的公式,提出了一种通用、简单可靠的高速宽带混频环防错锁方案,推导出了设计公式,并给出了工程设计实例,通过工程应用验证了结果的正确性。

Design of beacon system based on MSP430 micro- controller

In order to solve the onboard recorder search problem, a new beacon system based on radio direction finding tech- nique, which indicates the orientation of the recorder, is designed. The system consists of phase-locked loop （PLL）, micro- processor, global position system （GPS） module, power module and so on. The scene simulation verifies the feasibility and reliability of the system. This beacon system can be applied to the recorder search in many fields, and can effectively reduce the search scope and improve work efficiency.

微弱信号检测与锁定放大电路

介绍了一种微弱信号的检测与锁定放大方法。通过模拟锁相环工作锁定待检微弱信号的频率,利用控制器测量该锁相环的输出频率,并根据该频率值控制直接数字合成电路产生同频信号,该信号作为相关检测所需的参考信号。系统采用乘法器和积分电路实现相关检测,通过步进调整参考信号的相位,使互相关值最大,获得与被测信号同频同相的再生信号,从而实现微弱信号的检测与放大。该方法能够实现频率检测及幅度检测等功能。经实验测试表明:在低信噪比条件下,该方法仍具有较好的线性测量特性和较高的准确度,可实现任意波形的微弱信号自动检测和再生放大。

永磁直驱风电变流器无传感器控制研究

永磁直驱风力发电系统是一种新型的风力发电系统,具有广泛的应用前景。背靠背的全功率变流器是直驱型风力发电系统中的关键设备,既要实现对电网转换优质电能的功能,又要对永磁同步发电机(PMSG)进行控制。永磁同步发电机的无传感器控制技术具有重要的研究意义。根据永磁同步发电机的数学模型,利用其电磁、电气关系,提出了一种基于转子磁链闭环锁相环的永磁同步发电机位置的估算算法。通过仿真和实验结果表明,利用该估算方法能够准确计算出永磁同步发电机的位置,并可以利用其对永磁同步发电机实现有效的控制。

一种应用于软件定义互连系统的多协议SerDes电路

为满足片上系统的柔性互连,提出一种应用于软件定义互连系统的1.0625~10.3125Gbps多协议SerDes电路结构.该电路采用统一架构实现不同协议的规范需求,通过一种1×QPLL+4×Lane PLL的时钟结构实现宽频点和低抖动的时钟输出,通过可编程的发送端前向反馈均衡器和接收端线性均衡器和判决反馈均衡器电路,实现最大32dB的插损补偿.测试结果表明,所设计的SerDes电路在10.3125Gbps速率下发送总抖动为21.2ps,随机抖动均方根值为633.7fs,最大功耗29.33mW/Gbps,发送端眼图和接收端抖动容限及误码率均能够满足FC-PI-4,RapidIO 3.0,10GBase-KR,1000Base-X的协议规范要求.

A High-Speed Dual Modulus Prescaler Using 0.25 μm CMOS Technology

A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.

C波段频率合成器的设计

在分析常规数字锁相环路基础上，利用数字锁相混频环电路实现了C波段快速低相噪宽带频率合成器的设计，并进行了理论分析。给出的研制模块的指标测试结果，验证了理论分析的正确性。