The problem of improving the performance of min-sum decoding of low-density parity-check （LDPC） codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC cod...The problem of improving the performance of min-sum decoding of low-density parity-check （LDPC） codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC codes is proposed. The proposed algorithm modifies the variable node message in the iteration process by averaging the new message and previous message if their signs are different. Compared with the standard min-sum algorithm, the modification is achieved with only a small increase in complexity, but significantly improves decoding performance for both regular and irregular LDPC codes. Simulation results show that the performance of our modified decoding algorithm is very close to that of the standard sum-product algorithm for moderate length LDPC codes.展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
基金supported by the Major State Basic Research Development Program of China (2009CB320300)
文摘The problem of improving the performance of min-sum decoding of low-density parity-check （LDPC） codes is considered in this paper. Based on min-sum algorithm, a novel modified min-sum decoding algorithm for LDPC codes is proposed. The proposed algorithm modifies the variable node message in the iteration process by averaging the new message and previous message if their signs are different. Compared with the standard min-sum algorithm, the modification is achieved with only a small increase in complexity, but significantly improves decoding performance for both regular and irregular LDPC codes. Simulation results show that the performance of our modified decoding algorithm is very close to that of the standard sum-product algorithm for moderate length LDPC codes.
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
