RL and AHP-Based Multi-Timescale Multi-Clock Source Time Synchronization for Distribution Power Internet of Things

Time synchronization(TS)is crucial for ensuring the secure and reliable functioning of the distribution power Internet of Things(IoT).Multi-clock source time synchronization(MTS)has significant advantages of high reliability and accuracy but still faces challenges such as optimization of the multi-clock source selection and the clock source weight calculation at different timescales,and the coupling of synchronization latency jitter and pulse phase difference.In this paper,the multi-timescale MTS model is conducted,and the reinforcement learning(RL)and analytic hierarchy process(AHP)-based multi-timescale MTS algorithm is designed to improve the weighted summation of synchronization latency jitter standard deviation and average pulse phase difference.Specifically,the multi-clock source selection is optimized based on Softmax in the large timescale,and the clock source weight calculation is optimized based on lower confidence bound-assisted AHP in the small timescale.Simulation shows that the proposed algorithm can effectively reduce time synchronization delay standard deviation and average pulse phase difference.

Formal verification of synchronous data-flow program transformations toward certified compilers

Translation validation was invented in the 90＇s by Pnueli et al. as a technique to formally verify the correctness of code generators. Rather than certifying the code generator or exhaustively qualifying it, translation validators attempt to verify that program transformations preserve semantics. In this work, we adopt this approach to formally verify that the clock semantics and data dependence are preserved during the compilation of the Signal compiler. Translation valida- tion is implemented for every compilation phase from the initial phase until the latest phase where the executable code is generated, by proving the transformation in each phase of the compiler preserves the semantics. We represent the clock semantics, the data dependence of a program and its trans- formed counterpart as first-order formulas which are called clock models and synchronous dependence graphs （SDGs）, respectively. We then introduce clock refinement and depen- dence refinement relations which express the preservations of clock semantics and dependence, as a relation on clock mod- els and SDGs, respectively. Our validator does not require any instrumentation or modification of the compiler, nor any rewriting of the source program.