Research on Multi-Core Processor Analysis for WCET Estimation

Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field.

Hybridization of Metaheuristics Based Energy Efficient Scheduling Algorithm for Multi-Core Systems

The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,working environments,topologies,and so on.The existing multi-core technology unlocks additional research opportunities for energy minimization by the use of effective task scheduling.At the same time,the task scheduling process is yet to be explored in the multi-core systems.This paper presents a new hybrid genetic algorithm(GA)with a krill herd(KH)based energy-efficient scheduling techni-que for multi-core systems(GAKH-SMCS).The goal of the GAKH-SMCS tech-nique is to derive scheduling tasks in such a way to achieve faster completion time and minimum energy dissipation.The GAKH-SMCS model involves a multi-objectivefitness function using four parameters such as makespan,processor utilization,speedup,and energy consumption to schedule tasks proficiently.The performance of the GAKH-SMCS model has been validated against two datasets namely random dataset and benchmark dataset.The experimental outcome ensured the effectiveness of the GAKH-SMCS model interms of makespan,pro-cessor utilization,speedup,and energy consumption.The overall simulation results depicted that the presented GAKH-SMCS model achieves energy effi-ciency by optimal task scheduling process in MCS.

Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture

Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors.

Multi-Objective Optimization of Aluminum Alloy Electric Bus Frame Connectors for Enhanced Durability

The widespread adoption of aluminumalloy electric buses,known for their energy efficiency and eco-friendliness,faces a challenge due to the aluminum frame’s susceptibility to deformation compared to steel.This issue is further exacerbated by the stringent requirements imposed by the flammability and explosiveness of batteries,necessitating robust frame protection.Our study aims to optimize the connectors of aluminum alloy bus frames,emphasizing durability,energy efficiency,and safety.This research delves into Multi-Objective Coordinated Optimization(MCO)techniques for lightweight design in aluminum alloy bus body connectors.Our goal is to enhance lightweighting,reinforce energy absorption,and improve deformation resistance in connector components.Three typical aluminum alloy connectors were selected and a design optimization platform was built for their MCO using a variety of software and methods.Firstly,through three-point bending experiments and finite element analysis on three types of connector components,we identified optimized design parameters based on deformation patterns.Then,employing Optimal Latin hypercube design(OLHD),parametric modeling,and neural network approximation,we developed high-precision approximate models for the design parameters of each connector component,targeting energy absorption,mass,and logarithmic strain.Lastly,utilizing the Archive-based Micro Genetic Algorithm(AMGA),Multi-Objective Particle Swarm Optimization(MOPSO),and Non-dominated SortingGenetic Algorithm(NSGA2),we explored optimized design solutions for these joint components.Subsequently,we simulated joint assembly buckling during bus rollover crash scenarios to verify and analyze the optimized solutions in three-point bending simulations.Each joint component showcased a remarkable 30%–40%mass reduction while boosting energy absorption.Our design optimization method exhibits high efficiency and costeffectiveness.Leveraging contemporary automation technology,the design optimization platform developed in this study is poised to facilitate intelligent optimization of lightweight metal components in future applications.

Thermal stress simulation analysis of aerospace optical fibers and connectors and related extensions to high-speed railway area

Aerospace optical cables and fiber-optic connectors have numerous advantages(e.g.,low loss,wide transmission frequency band,large capacity,light weight,and excellent resistance to electromagnetic interference).They can achieve optical communication interconnections and high-speed bidirectional data transmission between optical terminals and photodetectors in space,ensuring the stability and reliability of data transmission during spacecraft operations in orbit.They have become essential components in high-speed networking and optically interconnected communications for spacecrafts.Thermal stress simulation analysis is important for evaluating the temperature stress concentration phenomenon resulting from temperature fluctuations,temperature gradients,and other factors in aerospace optical cables and connectors under the combined effects of extreme temperatures and vacuum environments.Considering this,advanced optical communication technology has been widely used in high-speed railway communication networks to transmit safe,stable and reliable signals,as high-speed railway optical communication in special areas with extreme climates,such as cold and high-temperature regions,requires high-reliability optical cables and connectors.Therefore,based on the finite element method,comprehensive comparisons were made between the thermal distributions of aerospace optical cables and J599III fiber optic connectors under different conditions,providing a theoretical basis for evaluating the performance of aerospace optical cables and connectors in space environments and meanwhile building a technical foundation for potential optical communication applications in the field of high-speed railways.

The Design of Multi-Connector IoT Central Gateway Based on Raspberry Pi and Docker

With the vigorous development of Internet of Things(IoT)technology,the demand for communication and data exchange between different types of IoT devices is increasing day by day.To solve the problems of diversity and complexity of communication protocols between devices,this paper proposes a design scheme of a multi-connector IoT central gateway based on Raspberry Pi and Docker.Through the research and application of related technologies,by integrating multiple communication interfaces and utilizing containerization technology,an efficient,flexible,and scalable IoT central gateway has been realized,which can support the connection and data interaction of multiple communication protocols and provide strong support for the stable operation and development of the IoT system.

Enrichment of Fetal Nucleated Red Blood Cells by Multi-core Magnetic Composite Particles for Non-invasive Prenatal Diagnosis

A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor（anti-CD71）, was prepared. The fetal nucleated red blood cells（FNRBCs） in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization（FISH） technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis.

Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips

A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.

Multi-core optimization for conjugate gradient benchmark on heterogeneous processors

Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.

Theoretical Analysis on Inter-Core Crosstalk Suppression Model for Multi-Core Fiber

Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly.

Modeling of Few-Mode Multi-Core Optical Fiber Channel Based on Non-Uniform Mode Field Distribution

In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results.

Cache performance optimization of irregular sparse matrix multiplication on modern multi-core CPU and GPU

This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the multiplier-matrix,and the other is caused by the multiplicand.For each of them,the paper puts forward an optimization method respectively.The first hash based method removes cache misses of the 1 st category effectively,and improves the performance by a factor of 6 on an Intel 8-core CPU for the best cases.For cache misses of the 2nd category,it proposes a new cache replacement algorithm,which achieves a cache hit rate much higher than other historical knowledge based algorithms,and the algorithm is applicable on CELL and GPU.To further verify the effectiveness of our methods,we implement our algorithm on GPU,and the performance perfectly scales with the size of on-chip storage.

Performance Behaviour Analysis of the Present 3-Level Cache System for Multi-Core Processors

In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core processors is developed and its possible performance has been analyzed with the increase in number of cores. Various important performance parameters like access time and utilization of individual cache at different level and overall average access time of the cache system is determined. Results for up to 1024 cores have been reported in this paper.

Parallel scheduling strategy of web-based spatial computing tasks in multi-core environment

In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of parallel processing mechanisms.One is that it can evenly allocate tasks to each server node in the cluster and the other is that it can implement the load balancing inside a server node.Based on the strategy,a new web-based spatial computing model is designed in this paper,in which,a task response ratio calculation method,a request queue buffer mechanism and a thread scheduling strategy are focused on.Experimental results show that the new model can fully use the multi-core computing advantage of each server node in the concurrent access environment and improve the average hits per second,average I/O Hits,CPU utilization and throughput.Using speed-up ratio to analyze the traditional model and the new one,the result shows that the new model has the best performance.The performance of the multi-core server nodes in the cluster is optimized;the resource utilization and the parallel processing capabilities are enhanced.The more CPU cores you have,the higher parallel processing capabilities will be obtained.

Performance Analysis for EDMA Based on TIC6678Multi-core DSP

Frequent data exchange among all kinds of memories has become an inevitable phenomenon in the process of modern embeddedsoftware design. In order to improve the ability of the embedded system data＇s throughput and computation, most embeddeddevices introduce Enhanced Direct Memory Access （EDMA） data transfer technology. TMS320C6678 is a multi-core DSPproduced by Texas Instruments （TI）. There are ten EDMA transmission controllers in the chip for configuration and datatransmissions are allowed to be performed between any two pieces of storage at the same time. This paper expounds the workingmechanism of EDMA based on multi-core DSP TMS320C6678. At the same time, multiple data sets are provided and thebottleneck of limiting data throughout is analyzed and solved.

The Channel Maps and the Position-Velocity Diagrams of Multi-core Structure of Cepheus C

The first important problem in the star forming process is the formation of proto star core in star forming regions of molecular cloud. The multi core structure in star forming regions is related to the forming of proto star core. The molecular radiation of C 18 O( J = 1-0) in Cepheus C has been observed. The C 18 O( J = 1-0) observations form the basis for an interesting study on the cloud cores and star formation activity in the cores of the Cepheus C. In order to study the multi core structure of C 18 O( J = 1-0) in the Cepheus C the channel maps and the position velocity diagrams of C 18 O( J = 1-0) will be shown. From the maps it is found that the contour level and distribution size of the three cores in Cepheus C are related to the channel velocity very much. The channel velocity of C 18 O( J = 1-0) molecules in core b, which distributed in all the channels velocity, is different with one in core a and core c very much. The C 18 O( J = 1-0) molecules in core a and core c of the Cepheus C mostly distributed in the blue shifted channel velocity relating to peak velocity, and only in -10.0 ～ -9.5 km/s, which is the red shifted channel velocity relating to peak velocity. And the contour level of C 18 O( J = 1-0) in -10.0 ～ -9.5 km/s is small and the distrbution size in the channel map is small. According to the position velocity diagrams the asymmetry of the distribution both blue shifted and red shifted components should reflect the asymmetry of the profile. From the diagrams it also is found that the contour level and the distribution size of the three cores are different from each other. Both results from the maps and diagrams are coincident with each other.

Parallel Processing Design for LTE PUSCH Demodulation and Decoding Based on Multi-Core Processor

The Long Term Evolution (LTE) system imposes high requirements for dispatching delay.Moreover,very large air interface rate of LTE requires good processing capability for the devices processing the baseband signals.Consequently,the single-core processor cannot meet the requirements of LTE system.This paper analyzes how to use multi-core processors to achieve parallel processing of uplink demodulation and decoding in LTE systems and designs an approach to parallel processing.The test results prove that this approach works quite well.

RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

Experimental investigation and analytically modeling of hysteretic behavior of rigid bus-flexible connectors of 220 kV electrical substations

This paper describes the quasi-static testing and analytical modelling of the hysteretic behavior of aluminum alloy rigid bus-flexible connectors of 220 kV electrical substations.The main objective of the study is to experimentally investigate the hysteretic behavior of six different types of rigid bus-flexible connectors 220 kV electrical substations when subjected to cyclic loading.Another objective is to theoretically study the flexibility and effectiveness of a previously proposed analytical model in fitting the experimental hysteresis loops of the tested rigid bus-flexible connectors.The experimental investigation indicates that the tested rigid bus-flexible connectors exhibit highly asymmetric hysteresis behavior along with tension stiffening effect.The theoretical study demonstrates that the generalized Bouc-Wen model has high flexibility and is effective in fitting the experimental hysteresis resisting force-displacement curves of the six tested rigid bus-flexible connectors.

基于SSTDR的光伏连接器故障检测

随着运行时间的增长,光伏连接器会出现氧化、老化、松动等现象,易导致接触不良、发热等问题,最终可能引起断路、电弧等故障,对光伏系统的高效、安全运行造成不良影响。由于光伏连接器故障会引起其等效阻抗的变化,该文采用扩频时域反射法(spread spectrum time domain reflectometry,SSTDR)来进行检测:通过向光伏连接器所在的光伏组件串注入正弦高频信号调制的伪随机序列序列测试信号,分析入射信号与反射信号的相关特性,再与健康状态下的特性进行比较,来实现光伏连接器故障在线诊断。对此进行仿真计算并在4块光伏板组成的光伏组串中进行实验,发现开路故障时包络面积最大可达到5×10^(5),而脱离故障时包络面积最小为0.8×10^(5),二者皆远大于健康时的包络面积0.07×10^(5),可有效诊断光伏连接器是否发生故障。