Integrated power electronics module based on chip scale packaged power devices

High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.

Structured Illumination Chip Based on Integrated Optics

A compact structured illumination chip based on integrated optics is proposed and fabricated on a silicon-on- insulator platform. Based on the simulation of Caussian beam interference, we adopt a chirped diffraction grating to achieve a specific interference pattern. The experimental results match well with the simulations. The portability and flexibility of the structured illumination chip can be increased greatly through horizontal encapsulation. High levels of integration, compared with the conventional structured illumination approach, make this chip very compact, with a footprint of only around 1 mm2. The chip has no optical lenses and can be easily combined with a microfluidic system. These properties would make the chip very suitable for portable 3D scanner and compact super-resolution microscopy applications.

A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.

Integrated Carbon Nanotubes Electrodes in Microfluidic Chip via MWPCVD

An on-chip electrochemical detector for microfluidic chips was described, based on integrated carbon nanotube （CNT） electrodes directly onto the chip substrate through microwave plasma chemical vapor deposition （MWPCVD）. The attractive performance of the integrated CNT electrodes was demonstrated for the amperometric detection of sucrose, glucose and D-fructose. The integrated CNT electrodes showed stronger electrocatalytic activity than gold electrodes.

Creating Distinctive Connections between Multifunctional Microwave Circuits and Mobile-Terminal Radio-Frequency Integrated Chips Using Integrated Passive Device Technology

In this review,the advanced microwave devices based on the integrated passive device(IPD)technology are expounded and discussed in detail,involving the performance breakthroughs and circuit innovations.Then,the development trend of IPD-based multifunctional microwave circuits is predicted further by analyzing the current research hot spots.This paper discusses a distinctive research area for microwave circuits and mobile-terminal radio-frequency integrated chips.

3D heterogeneous integration of wideband RF chips using silicon-based adapter board technology

An ultra-wideband mixing component cascaded by a mixing multi-function chip and a frequency multiplier multi-function chip was demonstrated and implemented using 3D heterogeneous integration based on the silicon adapter board technology.Four layers of high-resistance silicon substrate stack packaging are implemented based on the wafer-level gold-gold bonding process.Each layer adopts though silicon via(TSV)technology to realize signal interconnection.A core monolithic integrated microwave chip(MMIC)is embedded in the silicon cavity,and the silicon-based filter is integrated with the high-resistance silicon substrate.The interconnect line,cavity and filter of the silicon-based adapter board are designed with AutoCAD,and HFSS is adopted for 3D electromagnetic field simulation.According to the measured results,the radio frequency(RF)of the mixing multi-function chip is 40-44 GHz and its intermediate frequency(IF)can cover the Ku band with a chip size of 10 mm×11 mm×1 mm.The multiplier multi-function chip operates at 16-20 GHz.The fundamental suppression is greater than 50 dB and the second harmonic suppression is better than 40 dB with a chip size of 8 mm×8 mm×1 mm.The cascaded fully assembled mixing component achieves a spur of better than-50 dBc and a gain of better than 15 dB.

Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

Integrated Control System of Vehicle ABS/ASR/ACC Based onMC9S12DP256

The integrated control system of vehicle ABS/ASR/ACC has been developed using the MC9S12DP256 single chip, which is the new Motorola 16-bit product in HSC12 family. The system including the main control module, the data collection module and the drive and fault diagnosis module is demonstrated and its data collection function is presented in detail. The system designed by the modularization can supervise the data, drive the valves and pump. The program can be debugged on line, which is steady and reliable validated by the large numbers of vehicle road tests.

Optical transmitter module with hybrid integration of DFB laser diode and proton-exchanged LiNbO_(3)modulator chip

In this work,a hybrid integrated optical transmitter module was designed and fabricated.A proton-exchanged Mach–Zehnder lithium niobate(LiNbO_(3))modulator chip was chosen to enhance the output extinction ratio.A fiber was used to adjust the rotation of the polarization direction caused by the optical isolator.The whole optical path structure,including the laser chip,lens,fiber,and modulator chip,was simulated to achieve high optical output efficiency.After a series of process improvements,a module with an output extinction ratio of 34 dB and a bandwidth of 20.5 GHz(from 2 GHz)was obtained.The optical output efficiency of the whole module reached approximately 21%.The link performance of the module was also measured.

Monolithically Integrated Photonic Structures for Stable On-Chip Solar Blind Communications

A solar-blind multi-quantum well(MQW)structure wafer based on AlGaN materials is epitaxial growth by metal-organic chemical vapor deposition(MOCVD).The monolithically integrated photonic chips including light-emitting diodes(LEDs),waveguides,and photodetec-tors(PDs)are presented.The results of the finite-difference time-domain(FDTD)simulation confirm the strong light constraint of the wave-guide designed with the triangular structure in the optical coupling region.Furthermore,in virtue of predominant ultraviolet transverse mag-netic(TM)modes,the solar blind optical signal is more conducive to lateral transmission along the waveguide inside the integrated chip.The integrated PDs demonstrate sufficient photosensitivity to the optical signal from the integrated LEDs.When the LEDs are operated at 100 mA current,the photo-to-dark current ratio(PDCR)of the integrated PD is about seven orders of magnitude.The responsivity,specific detectivity,and external quantum efficiency of the integrated self-driven PD are 74.89 A/W,4.22×1013 Jones,and 3.38×104%,respectively.The stable on-chip optical information transmission capability of the monolithically integrated photonic chips confirms the great potential for application in large-scale on-chip optical communication in the future.

Flip Chip技术在集成电路封装中的应用

阐述从集成电路封装发展现状、Flip Chip技术内涵、Flip Chip技术在集成电路封装中的应用剖析、市场发展展望等多个角度,探讨在集成电路封装中,应用Flip Chip技术的必要性和重要性。

FlexMEMS-enabled hetero-integration for monolithic FBAR-above-IC oscillators

In this work,a monolithic oscillator chip is heterogeneously integrated by a film bulk acoustic resonator(FBAR)and a complementary metal-oxide-semiconductor(CMOS)chip using FlexMEMS technology.In the 3 D-stacked integrated chip,the thin-film FBAR sits directly over the CMOS chip,between which a 4μm-thick SU-8 layer provides a robust adhesion and acoustic reflection cavity.The proposed system-on-chip(SoC)integration features a simple fabrication process,small size,and excellent performance.The oscillator outputs 2.024 GHz oscillations of-13.79 dB m and exhibits phase noises of-63,-120,and-136 dB c/Hz at 1 kHz,100 kHz,and far-from-carrier offset,respectively.FlexMEMS technology guarantees compact and accurate assembly,process compatibility,and high performance,thereby demonstrating its great potential in SoC hetero-integration applications.

Flip Chip结构的IC信号完整性仿真分析

针对Flip Chip封装型芯片设计过程中存在的传输线阻抗不连续与串扰过大等问题,从层叠设置与板材介质厚度两个角度提出了一种基于阻抗、串扰的仿真分析设计方法,主要涉及两个方面:对于由信号参考平面被分割而造成的阻抗突变问题,通过添加参考平面而使信号具有完整的回流路径,使得传输线的阻抗在平面分割处由167.5Ω降至52.5Ω;对于因布线密度过大而造成的走线之间的串扰系数偏高的问题,通过减小板材的介质厚度使传输线间串扰系数的最大值从17.26%降至14.01%。仿真结果表明,此设计方法有效降低了芯片设计中潜在的信号完整性风险,提高了芯片的可靠性和稳定性。

Study on the Development of the Chip Information Industry Based on Moore’s Law

Chips are the carriers of ICs (integrated circuits). As a result of design, manufacturing, and packaging and testing processes, chips are typically wholly independent entities intended for immediate use. According to known data, one unit of chip output can drive up to ten units of output in the electronic information industry and 100 units of GDP (Gross Domestic Product). The Chip Information Industry is a strategic industry in most developed countries in Europe and North America. The development of the Chip Information Industry is related to national economies and personal livelihoods. Moore discovered a certain trend after analyzing data: in general, every newly produced chip has twice the capacity of the previous generation, and it takes 18 to 24 months for the next generation to be subsequently invented. This trend has come to be known as Moore’s Law. It applies not only to the development of memory chips but also to the evolutionary paths of processor capability and disk drive storage capacity. Moore’s Law has become the basis of performance prediction in several industries. However, since 2011, the size of silicon transistors has been approaching its physical limit at the atomic level. Due to the nature of silicon, additional breakthroughs in the running speed and performance of silicon transistors are severely limited. Elevated temperature and leakage are the two main sources that invalidate Moore’s Law. To counter these issues, This paper analyzes specific problems challenges in the Chip Information Industry, including the development of carbon nanotube chips and fierce competition in the international Chip Information Industry. In addition, this paper undertakes a critical analysis of the Chinese Chip Information Industry and countermeasures to Chinese Chip Information Industry development.

A Single-Chip UHF RFID Reader Transceiver IC

A single-chip UHF RFID reader transceiver IC has been implemented in 0.18 μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2C with fully-compliant China 800/900 MHz RFID draft, ISO/IEC 18000-6C protocol and ETSI 302 208-1 local regulation. The normal mode receiver in the presence of -3 dBm self-jammer achieves -75 dBm 1% PER sensitivity. The linear class-A PA integrated in transmitter has 25 dBm OP1 dB output power for CW. The fully-integrated fractional-N fre-quency synthesizer is designed based on MASH 1-1-1 sigma-delta modulator and 1.8 GHz fundamental frequency LC-VCO for lower in-band and out-of-band phase noise. The measured phase noise is up to -106 dBc/Hz@200 kHz and -131 dBc/Hz@1 MHz offset from center frequency and the integrated RMS jitter from 10 kHz to 10 MHz is less than 1.6 pS. The chip dissipates 330 mA from 3.3 V power supply when transmitting 22.4 dBm CW signal and the PAE of linear PA is up to 26%. The chip die area is 16.8 mm2.

Signal and Power Integrity Challenges for High Density System-on-Package

As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.

基于AT89S52单片机的稻作区智能灌溉控制系统设计

【目的】克服稻作区田间难以铺设电路等难题,实现田间灌溉无人化,提高安徽省稻作区灌溉智能化和精准化水平,探索利用新一代电子信息技术实现智能灌溉的可行性。【方法】本文设计了一种基于AT89S52单片机的稻作区智能灌溉控制系统,包括一体化提拉式水闸、灌溉硬件子系统和灌溉软件子系统。闸门采用一体化设计,集成了以AT89S52单片机为控制器的中央处理单元模块、传感器感知模块和太阳能供电模块;以Keil C语言开发了闸门终端控制软件,以C++语言开发了系统上位机控制软件。【结果】应用试验表明,本系统运行安全稳定,电机自动控制响应时间<1 s,闸门开度控制误差<1.5 mm,闸前、后水位控制误差<8 mm,数据传输丢包率最大为0.11%,自由出流状态下闸门流量计算误差<1%,淹没出流状态下闸门流量计算误差<1.2%。【结论】本系统运行安全稳定,在室外环境条件下响应速度快,可满足稻作区田间灌溉复杂环境下用水智能化和精准化的要求。

光储备池通感一体通信噪声抑制方案(封面文章·特邀)

通感一体技术可利用已大范围铺设的光纤网实现智能传感,具备智能识别、信息融合优势。在同波长通感共传信道中,通感信号串扰及光纤传输噪声严重影响通信信号质量,需提升发射功率来保证低误码率,但增大了非线性噪声和功耗。提出了基于光储备池计算神经网络的通感共传信道通信失真均衡方法,搭建了信道均衡仿真系统,实现了低发射功率下前向通信信号噪声均衡。周期线性调频光和56 Gb/s四电平脉冲幅度调制信号分别用于分布式瑞利散射传感和数据通信。仿真结果表明,在5~14 dBm入纤功率时,与未均衡信号相比该方法可提供高于3个数量级以上的误码率优化。此方法在短距离模块间15~24 km光纤传输和0.5~2.0 GHz带宽线性调频感测脉冲下均实现了2个数量级以上的误码率下降。依托光储备池计算芯片的低能耗和低延时优势,该方法可为进一步提升通感一体系统中噪声抑制能力提供理论支撑。

光子神经网络研究进展

在数据海量化、信息化的时代,电子计算机处理系统所面临的算力和能耗等性能要求愈发严苛,传统冯·诺依曼架构存在“内存墙”和“功耗墙”瓶颈,加之摩尔定律放缓甚至失效,使得电子芯片在计算速度和功耗方面遇到极大挑战,利用光计算替代传统电子计算将是解决当前算力与功耗问题的极具潜力的途径之一。本文系统地梳理了片上集成和自由空间的光子神经网络架构与算法方面的研究进展,详细介绍了典型的研究工作,然后讨论并对比了这两种光子神经网络的优劣势,以及光子神经网络的训练策略等。最后探讨了光子神经网络面临的挑战,并对其未来发展进行了前瞻性的展望。