Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter....Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.展开更多
This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chi...This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.展开更多
An improved single-π equivalent circuit model for on-chip inductors in the GaAs process is presented in this paper. Considering high order parasites, the model is established by comprising an improved skin effect bra...An improved single-π equivalent circuit model for on-chip inductors in the GaAs process is presented in this paper. Considering high order parasites, the model is established by comprising an improved skin effect branch and a substrate lateral coupling branch. The parameter extraction is based on an improved characteristic function approach and vector fitting method. The model has better simulation than the previous work over the measured data of 2.5r and 4.5r on-chip inductors in the GaAs process.展开更多
A 2 5GHz fully integrated LC VCO is fabricated in a standard single poly 4 metal 0 35μm digital CMOS process,using a complementary cross coupled topology for lowering power dissipation and reducing the effect of...A 2 5GHz fully integrated LC VCO is fabricated in a standard single poly 4 metal 0 35μm digital CMOS process,using a complementary cross coupled topology for lowering power dissipation and reducing the effect of 1/ f noise.An on chip LC filtering technique is used to lower the high frequency noise.Accumulation varactors are used to widen frequency tuning.The measured tuning range is 23 percent.A single hexadecagon symmetric on chip spiral is used with grounded shield pattern to reduce the chip area and maximize the quality factor.A phase noise of -118dBc/Hz at 1MHz offset is measured.The power dissipation is 4mA at V DD =3 3V.展开更多
文摘Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.
文摘This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.
基金Project supported by the National Natural Science Foundation of China(No.61674036)
文摘An improved single-π equivalent circuit model for on-chip inductors in the GaAs process is presented in this paper. Considering high order parasites, the model is established by comprising an improved skin effect branch and a substrate lateral coupling branch. The parameter extraction is based on an improved characteristic function approach and vector fitting method. The model has better simulation than the previous work over the measured data of 2.5r and 4.5r on-chip inductors in the GaAs process.
文摘A 2 5GHz fully integrated LC VCO is fabricated in a standard single poly 4 metal 0 35μm digital CMOS process,using a complementary cross coupled topology for lowering power dissipation and reducing the effect of 1/ f noise.An on chip LC filtering technique is used to lower the high frequency noise.Accumulation varactors are used to widen frequency tuning.The measured tuning range is 23 percent.A single hexadecagon symmetric on chip spiral is used with grounded shield pattern to reduce the chip area and maximize the quality factor.A phase noise of -118dBc/Hz at 1MHz offset is measured.The power dissipation is 4mA at V DD =3 3V.
