A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

基于E-TSPC技术的10 GHz低功耗多模分频器的设计

基于扩展的真单相时钟（E-TSPC）技术,设计了一款用于10 GHz扩频时钟发生器（SSCG）的分频比范围为32~63的多模分频器（MMD）。在设计中,基于D触发器的2/3分频器采用了动态E-TSPC技术,这不仅降低了功耗和芯片面积,而且改善了最高工作频率。MMD由5级2/3分频器级联而成,由5 bit数字码控制。详细介绍和讨论了2/3分频器和MMD的工作原理和优势。MMD是SSCG的一部分,采用55 nm CMOS工艺进行了流片,芯片面积为35μm×10μm,电源电压为1.2 V,最高工作频率为10 GHz,此时功耗为1.56 m W。

Pulse swallowing frequency divider with low power and compact structure

A pulse swallowing frequency divider with low power and compact structure is presented.One of the DFFs in the divided by 2/3 prescaier is controlled by the modulus control signal,and automatically powered off when it has no contribution to the operation of the prescaier.The DFFs in the program counter and the swallow counter are shared to compose a compact structure,which reduces the power consumption further.The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28×22μm;.The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

基于CMOS工艺的9GHz~18GHz宽带高速多模分频器设计

在毫米波锁相环频率合成器中,压控振荡器输出的高频信号通常需要经过预分频后输入至多模分频器进行连续整数分频,而提高多模分频器的工作频率以减少预分频器级数可以提高锁相环系统的相位噪声性能。为实现高频环境下的连续整数分频功能,介绍了一种基于55nm CMOS工艺的9GHz~18GHz宽带高速可编程多模分频器的设计。该设计采用多级2/3分频器级联结构,通过控制有效的级联级数扩展分频范围,使之可实现16~524287连续分频比,通过采用电流模逻辑和扩展真单相时钟技术提高了工作频率。完成了版图绘制和寄生参数的提取仿真,后仿真结果显示,整体电路实现了9GHz~18GHz的工作频率范围。当输入信号被分频至100MHz输出时,相位噪声约为-142dBc/Hz@1kHz,具有高频率、大带宽、低相位噪声的优点。