Owing to wide applications of automatic control systems in the process industries, the impacts of controller performance on industrial processes are becoming increasingly significant. Consequently, controller maintena...Owing to wide applications of automatic control systems in the process industries, the impacts of controller performance on industrial processes are becoming increasingly significant. Consequently, controller maintenance is critical to guarantee routine operations of industrial processes. The workflow of controller maintenance generally involves the following steps: monitor operating controller performance and detect performance degradation, diagnose probable root causes of control system malfunctions, and take specific actions to resolve associated problems. In this article, a comprehensive overview of the mainstream of control loop monitoring and diagnosis is provided, and some existing problems are also analyzed and discussed. From the viewpoint of synthesizing abundant information in the context of big data, some prospective ideas and promising methods are outlined to potentially solve problems in industrial applications.展开更多
A bottleneck automatic identification algorithm based on loop detector data is proposed. The proposed algorithm selects the critical flow rate as the trigger variable of the algorithm which is calculated by the road c...A bottleneck automatic identification algorithm based on loop detector data is proposed. The proposed algorithm selects the critical flow rate as the trigger variable of the algorithm which is calculated by the road conditions the level of service and the proportion of trucks.The process of identification includes two parts. One is to identify the upstream of the bottleneck by comparing the distance between the current occupancy rate and the mean value of the occupancy rate and the variance of the occupancy rate.The other process is to identify the downstream of the bottleneck by calculating the difference of the upstream occupancy rate with that of the downstream.In addition the algorithm evaluation standards which are based on the time interval of the data the detection rate and the false alarm rate are discussed.The proposed algorithm is applied to detect the bottleneck locations in the Shanghai Inner Ring Viaduct Dabaishu-Guangzhong road section.The proposed method has a good performance in improving the accuracy and efficiency of bottleneck identification.展开更多
This paper addresses a computationally compact and statistically optimal joint Maximum a Posteriori(MAP)algorithm for channel estimation and data detection in the presence of Phase Noise(PHN)in iterative Orthogonal Fr...This paper addresses a computationally compact and statistically optimal joint Maximum a Posteriori(MAP)algorithm for channel estimation and data detection in the presence of Phase Noise(PHN)in iterative Orthogonal Frequency Division Multiplexing(OFDM)receivers used for high speed and high spectral efficient wireless communication systems.The MAP cost function for joint estimation and detection is derived and optimized further with the proposed cyclic gradient descent optimization algorithm.The proposed joint estimation and detection algorithm relaxes the restriction of small PHN assumptions and utilizes the prior statistical knowledge of PHN spectral components to produce a statistically optimal solution.The frequency-domain estimation of Channel Transfer Function(CTF)in frequency selective fading makes the method simpler,compared with the estimation of Channel Impulse Response(CIR)in the time domain.Two different time-varying PHN models,produced by Free Running Oscillator(FRO)and Phase-Locked Loop(PLL)oscillator,are presented and compared for performance difference with proposed OFDM receiver.Simulation results for joint MAP channel estimation are compared with Cramer-Rao Lower Bound(CRLB),and the simulation results for joint MAP data detection are compared with“NO PHN"performance to demonstrate that the proposed joint MAP estimation and detection algorithm achieve near-optimum performance even under multipath channel fading.展开更多
In the synthesis of the control algorithm for complex systems, we are often faced with imprecise or unknown mathematical models of the dynamical systems, or even with problems in finding a mathematical model of the sy...In the synthesis of the control algorithm for complex systems, we are often faced with imprecise or unknown mathematical models of the dynamical systems, or even with problems in finding a mathematical model of the system in the open loop. To tackle these difficulties, an approach of data-driven model identification and control algorithm design based on the maximum stability degree criterion is proposed in this paper. The data-driven model identification procedure supposes the finding of the mathematical model of the system based on the undamped transient response of the closed-loop system. The system is approximated with the inertial model, where the coefficients are calculated based on the values of the critical transfer coefficient, oscillation amplitude and period of the underdamped response of the closed-loop system. The data driven control design supposes that the tuning parameters of the controller are calculated based on the parameters obtained from the previous step of system identification and there are presented the expressions for the calculation of the tuning parameters. The obtained results of data-driven model identification and algorithm for synthesis the controller were verified by computer simulation.展开更多
A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency div...A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.展开更多
The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, ...The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.展开更多
A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency de...A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.展开更多
To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerati...To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerative PN ranging clock recovery is adopted. The CTL is a modified data transition tracking loop （DTTL）. The difference between them is that the Q channel output of the CTL is directly multiplied by a clock component, while that of the DTTL is multiplied by the Ⅰ channel transition detector output. Under the condition of a quasi-squareware PN ranging code, the tracking （ mean square timing jitter） performance of the CTL is analyzed. The tracking performances of the CTL and the DTTL, are compared over a wide range of symbol SNRs. The result shows that the CTL and the DTTL have the same performance at a large symbol SNR, while at a low symbol SNR, the former offers a noticeable enhancement.展开更多
A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the cente...A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.展开更多
基金Supported by the National Basic Research Program of China(2012CB720505)the National Natural Science Foundation of China(21276137,61433001)+1 种基金Tsinghua University Initiative Scientific Research Programthe seventh framework programme(FP7-PEOPLE-2013-IRSES-612230)of European Union
文摘Owing to wide applications of automatic control systems in the process industries, the impacts of controller performance on industrial processes are becoming increasingly significant. Consequently, controller maintenance is critical to guarantee routine operations of industrial processes. The workflow of controller maintenance generally involves the following steps: monitor operating controller performance and detect performance degradation, diagnose probable root causes of control system malfunctions, and take specific actions to resolve associated problems. In this article, a comprehensive overview of the mainstream of control loop monitoring and diagnosis is provided, and some existing problems are also analyzed and discussed. From the viewpoint of synthesizing abundant information in the context of big data, some prospective ideas and promising methods are outlined to potentially solve problems in industrial applications.
文摘A bottleneck automatic identification algorithm based on loop detector data is proposed. The proposed algorithm selects the critical flow rate as the trigger variable of the algorithm which is calculated by the road conditions the level of service and the proportion of trucks.The process of identification includes two parts. One is to identify the upstream of the bottleneck by comparing the distance between the current occupancy rate and the mean value of the occupancy rate and the variance of the occupancy rate.The other process is to identify the downstream of the bottleneck by calculating the difference of the upstream occupancy rate with that of the downstream.In addition the algorithm evaluation standards which are based on the time interval of the data the detection rate and the false alarm rate are discussed.The proposed algorithm is applied to detect the bottleneck locations in the Shanghai Inner Ring Viaduct Dabaishu-Guangzhong road section.The proposed method has a good performance in improving the accuracy and efficiency of bottleneck identification.
文摘This paper addresses a computationally compact and statistically optimal joint Maximum a Posteriori(MAP)algorithm for channel estimation and data detection in the presence of Phase Noise(PHN)in iterative Orthogonal Frequency Division Multiplexing(OFDM)receivers used for high speed and high spectral efficient wireless communication systems.The MAP cost function for joint estimation and detection is derived and optimized further with the proposed cyclic gradient descent optimization algorithm.The proposed joint estimation and detection algorithm relaxes the restriction of small PHN assumptions and utilizes the prior statistical knowledge of PHN spectral components to produce a statistically optimal solution.The frequency-domain estimation of Channel Transfer Function(CTF)in frequency selective fading makes the method simpler,compared with the estimation of Channel Impulse Response(CIR)in the time domain.Two different time-varying PHN models,produced by Free Running Oscillator(FRO)and Phase-Locked Loop(PLL)oscillator,are presented and compared for performance difference with proposed OFDM receiver.Simulation results for joint MAP channel estimation are compared with Cramer-Rao Lower Bound(CRLB),and the simulation results for joint MAP data detection are compared with“NO PHN"performance to demonstrate that the proposed joint MAP estimation and detection algorithm achieve near-optimum performance even under multipath channel fading.
文摘In the synthesis of the control algorithm for complex systems, we are often faced with imprecise or unknown mathematical models of the dynamical systems, or even with problems in finding a mathematical model of the system in the open loop. To tackle these difficulties, an approach of data-driven model identification and control algorithm design based on the maximum stability degree criterion is proposed in this paper. The data-driven model identification procedure supposes the finding of the mathematical model of the system based on the undamped transient response of the closed-loop system. The system is approximated with the inertial model, where the coefficients are calculated based on the values of the critical transfer coefficient, oscillation amplitude and period of the underdamped response of the closed-loop system. The data driven control design supposes that the tuning parameters of the controller are calculated based on the parameters obtained from the previous step of system identification and there are presented the expressions for the calculation of the tuning parameters. The obtained results of data-driven model identification and algorithm for synthesis the controller were verified by computer simulation.
文摘A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.
文摘The design of a 2. 488 Gbit/s clock and data recovery （CDR） If for synchronous digital hierarchy （SDH） STM-16 receiver is described. Based on the injected phase-locked loop （IPLL） and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 μan complementary metal-oxide-semiconductor （CMOS） technology. With 2^31 -1 pseudorandom bit sequences （PRBS） input, the sensitivity of data recovery circuit is less than 20 mV with 10^-12 bit error rate （BER）. The recovered clock shows a root mean square （rms） jitter of 2. 8 ps and a phase noise of - 110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1.49 mm × 1 mm.
文摘A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.
文摘To improve the performance of composite pseudo-noise （PN） code clock recovery in a regenerative PN ranging system at a low symbol signal-to-noise ratio （SNR）, a novel chip tracking loop （CTL） used for regenerative PN ranging clock recovery is adopted. The CTL is a modified data transition tracking loop （DTTL）. The difference between them is that the Q channel output of the CTL is directly multiplied by a clock component, while that of the DTTL is multiplied by the Ⅰ channel transition detector output. Under the condition of a quasi-squareware PN ranging code, the tracking （ mean square timing jitter） performance of the CTL is analyzed. The tracking performances of the CTL and the DTTL, are compared over a wide range of symbol SNRs. The result shows that the CTL and the DTTL have the same performance at a large symbol SNR, while at a low symbol SNR, the former offers a noticeable enhancement.
文摘A 2.5Gb/s/ch data recovery （DR） circuit is designed for an SFI-5 interface. To make the parallel data bit-synchronization and reduce the bit error rate （BER） ,a delay locked loop （DLL） is used to place the center of the data eye exactly at the rising edge of the data-sampling clock. A single channel DR circuit was fabricated in TSMC＇s standard 0. 18μm CMOS process. The chip area is 0. 46mm^2. With a 2^32 - 1 pseudorandom bit sequence （PRBS） input,the RMS jitter of the recovered 2.5Gb/s data is 3.3ps. The sensitivity of the single channel DR is less than 20mV with 10-12 BER.
