In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard ...In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard transform and 2 ×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities the proposed design merges the architectures processing individual transforms into a high-performance multi-transform coding architecture.Using a semiconductor manufacturing international corporation SMIC 0.18 μm complementary metal oxide semiconductor CMOS technology the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800 ×106 pixel/s with the hardware cost of 3 704 gates.The results demonstrate that the data throughput rate per unit area DTUA of this design is at least 40.28%higher than that of the reference design.This design can meet the requirements of real-time decoding digital cinema video 4 096 ×2 048@30 Hz at 62.9 MHz which helps to reduce the power consumption.展开更多
基金The National Key Technology R&D Program of China during the 12th Five Year Plan Period(No.2013BAJ05B03)
文摘In order to increase the hardware utilization and minimize the chip area a multi-transform coding architecture which includes 4 ×4 forward integer transform 4 ×4 inverse integer transform 4 ×4 Hadamard transform and 2 ×2 Hadamard transform is proposed. By simplifying these transforms and exploring their similarities the proposed design merges the architectures processing individual transforms into a high-performance multi-transform coding architecture.Using a semiconductor manufacturing international corporation SMIC 0.18 μm complementary metal oxide semiconductor CMOS technology the proposed architecture achieves the maximum operating clock frequency of 200 MHz and the throughput rate of 800 ×106 pixel/s with the hardware cost of 3 704 gates.The results demonstrate that the data throughput rate per unit area DTUA of this design is at least 40.28%higher than that of the reference design.This design can meet the requirements of real-time decoding digital cinema video 4 096 ×2 048@30 Hz at 62.9 MHz which helps to reduce the power consumption.
