Importance analysis quantifies the critical degree of individual component. Compared with the traditional binary state system,importance analysis of the multi-state system is more aligned with the practice. Because th...Importance analysis quantifies the critical degree of individual component. Compared with the traditional binary state system,importance analysis of the multi-state system is more aligned with the practice. Because the multi-valued decision diagram( MDD) can reflect the relationship between the components and the system state bilaterally, it was introduced into the reliability calculation of the multi-state system( MSS). The building method,simplified criteria,and path search and probability algorithm of MSS structure function MDD were given,and the reliability of the system was calculated. The computing methods of importance based on MDD and direct partial logic derivatives( DPLD) were presented. The diesel engine fuel supply system was taken as an example to illustrate the proposed method. The results show that not only the probability of the system in each state can be easily obtained,but also the influence degree of each component and its state on the system reliability can be obtained,which is conducive to the condition monitoring and structure optimization of the system.展开更多
The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital de...The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.展开更多
In order to improve the circuit complexity and reduce the long latency of B-1 operations,a novel B-1 operation in Galois Field GF(24)is presented and the corresponding systolic realization based on multiple-valued log...In order to improve the circuit complexity and reduce the long latency of B-1 operations,a novel B-1 operation in Galois Field GF(24)is presented and the corresponding systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure employs multiplevalued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the initial delay and the transistor and wire counts.The performance is evaluated by HSPICE simulation in 0.18μm CMOS technology and a comparison is conducted between our proposed implementation and those reported in the literature.The initial delay and the sum of transistors and wires in our MVL design are about 43%and 13%lower,respectively,in comparison with other corresponding binary CMOS implementations.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementations.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2k).展开更多
Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models bec...Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.展开更多
A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by ...A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the transistor and wire counts,and the initial delay.The performance is evaluated by HSPICE simulation with 0.18.μm CMOS technology.A comparison is conducted between our proposed implementation and those reported in the literature.The transistor counts,the wire counts and the initial delay in our MVL design show savings of about 23%,45%,and 72%,in comparison with the corresponding binary CMOS implementation.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2^k).展开更多
The idea that approximate exactness is the most we can and should expect scientific theories to yield underlies the formation and application of the multi-valued logic of approximation discussed in this paper. In this...The idea that approximate exactness is the most we can and should expect scientific theories to yield underlies the formation and application of the multi-valued logic of approximation discussed in this paper. In this logic, inexactness （measured by truth values） is controlled and minimized by means of uniquely designed deductions. We show how the notion of equality （including substitution of equals） is handled within this logic and we apply it to certain principles and interpretations of quantum theory.展开更多
Two-dimensional van der Waals(2D vdW)material-based heterostructure devices have been widely studied for high-end electronic applications owing to their heterojunction properties.In this study,we demonstrate graphene(...Two-dimensional van der Waals(2D vdW)material-based heterostructure devices have been widely studied for high-end electronic applications owing to their heterojunction properties.In this study,we demonstrate graphene(Gr)-bridge heterostructure devices consisting of laterally series-connected ambipolar semiconductor/Gr-bridge/n-type molybdenum disulfide as a channel material for field-effect transistors(FET).Unlike conventional FET operation,our Gr-bridge devices exhibit nonclassical transfer characteristics(humped transfer curve),thus possessing a negative differential transconductance.These phenomena are interpreted as the operating behavior in two series-connected FETs,and they result from the gate-tunable contact capacity of the Gr-bridge layer.Multi-value logic inverters and frequency tripler circuits are successfully demonstrated using ambipolar semiconductors with narrow-and wide-bandgap materials as more advanced circuit applications based on non-classical transfer characteristics.Thus,we believe that our innovative and straightforward device structure engineering will be a promising technique for future multi-functional circuit applications of 2D nanoelectronics.展开更多
This paper proposes the use of the current signal to express logic values and establishes the theory of grounded current switches suitable for I2L circuits.Based on the advantage that current signals are easy to be ad...This paper proposes the use of the current signal to express logic values and establishes the theory of grounded current switches suitable for I2L circuits.Based on the advantage that current signals are easy to be added, the design technique of I2L circuits by means of the multi-valued current signal is proposed.It is shown that simpler structure of I2L circuits can be obtained with this technique.展开更多
To enhance the expressive power and the declarative ability of a deductive database, various CWA (Closed World Assumption) formalizations including the naive CWA, the generalized CWA and the careful CWA are extended ...To enhance the expressive power and the declarative ability of a deductive database, various CWA (Closed World Assumption) formalizations including the naive CWA, the generalized CWA and the careful CWA are extended to multi-valued logics. The basic idea is to embed logic formulas into some polynomial ring. The extensions can be applied in a uniform manner to any finitely multi-valued logics. Therefore they are also of computational significance.展开更多
In cryptology, it is an important topic to study the best affine approach of functions. The best affine approach of Boolean functions has been discussed in ref. [1] by using the Walsh spectrum, of which the key proble...In cryptology, it is an important topic to study the best affine approach of functions. The best affine approach of Boolean functions has been discussed in ref. [1] by using the Walsh spectrum, of which the key problem is how to represent the correspondence of Boolean functions by using Walsh spectrum. For the multi-valued logical functions so far, the spectral representation of their correspondence has not been presented yet. This let-展开更多
A semantic model based on modal logic is proposed in the paperfor the enterprise viewpoint of ODP system. This model formalized the coop-eration relationship among objects within an ODP system. To handle the se-mantic...A semantic model based on modal logic is proposed in the paperfor the enterprise viewpoint of ODP system. This model formalized the coop-eration relationship among objects within an ODP system. To handle the se-mantic contradiction occurred in federation展开更多
Neurons with complex-valued weights have stronger capability because of their multi-valued threshold logic. Neurons with such features may be suitable for solution of different kinds of problems including associative ...Neurons with complex-valued weights have stronger capability because of their multi-valued threshold logic. Neurons with such features may be suitable for solution of different kinds of problems including associative memory,image recognition and digital logical mapping. In this paper,robustness or tolerance is introduced and newly defined for this kind of neuron ac-cording to both their mathematical model and the perceptron neuron's definition of robustness. Also,the most robust design for basic digital logics of multiple variables is proposed based on these robust neurons. Our proof procedure shows that,in robust design each weight only takes the value of i or -i,while the value of threshold is with respect to the number of variables. The results demonstrate the validity and simplicity of using robust neurons for realizing arbitrary digital logical functions.展开更多
A lot of research has been done on multiple-valued logic(MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube f...A lot of research has been done on multiple-valued logic(MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors(CNTFETs) are considered a viable alternative for silicon transistors(MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.展开更多
This paper analyses the binary expression of ternary signals and the binary construction of circuits, and proposes the design of a mixed-valued counter by using both binary flip-flops and ternary flip-flops ("tri...This paper analyses the binary expression of ternary signals and the binary construction of circuits, and proposes the design of a mixed-valued counter by using both binary flip-flops and ternary flip-flops ("tri-flops"). Here a new design of an 8421 BCD up-counter based on the mixed-valued binary-binary-ternary-coded decimal (B2TCD) code using mixed-valued logic is presented.展开更多
基金National Natural Science Foundation of China(No.61164009)the Science and Technology Research Project,Department of Education of Jiangxi Province,China(No.GJJ14420)Natural Science Foundation of Jiangxi Province,China(No.20132BAB206026)
文摘Importance analysis quantifies the critical degree of individual component. Compared with the traditional binary state system,importance analysis of the multi-state system is more aligned with the practice. Because the multi-valued decision diagram( MDD) can reflect the relationship between the components and the system state bilaterally, it was introduced into the reliability calculation of the multi-state system( MSS). The building method,simplified criteria,and path search and probability algorithm of MSS structure function MDD were given,and the reliability of the system was calculated. The computing methods of importance based on MDD and direct partial logic derivatives( DPLD) were presented. The diesel engine fuel supply system was taken as an example to illustrate the proposed method. The results show that not only the probability of the system in each state can be easily obtained,but also the influence degree of each component and its state on the system reliability can be obtained,which is conducive to the condition monitoring and structure optimization of the system.
文摘The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.
基金Supported by the National Natural Science Foundation of China(61801027)。
文摘In order to improve the circuit complexity and reduce the long latency of B-1 operations,a novel B-1 operation in Galois Field GF(24)is presented and the corresponding systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure employs multiplevalued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the initial delay and the transistor and wire counts.The performance is evaluated by HSPICE simulation in 0.18μm CMOS technology and a comparison is conducted between our proposed implementation and those reported in the literature.The initial delay and the sum of transistors and wires in our MVL design are about 43%and 13%lower,respectively,in comparison with other corresponding binary CMOS implementations.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementations.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2k).
文摘Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.
基金National Natural Science Foundation of China(61801027)。
文摘A new AB^2 operation in Galois Field GF(24)is presented and its systolic realization based on multiple-valued logic(MVL)is proposed.The systolic structure of the operation employs multiple-valued current mode(MVCM)by using dynamic source-coupled logic(SCL)to reduce the transistor and wire counts,and the initial delay.The performance is evaluated by HSPICE simulation with 0.18.μm CMOS technology.A comparison is conducted between our proposed implementation and those reported in the literature.The transistor counts,the wire counts and the initial delay in our MVL design show savings of about 23%,45%,and 72%,in comparison with the corresponding binary CMOS implementation.The systolic architecture proposed is simple,regular,and modular,well suited for very large scale integration(VLSI)implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be a potential solution for high performance arithmetic operations in GF(2^k).
文摘The idea that approximate exactness is the most we can and should expect scientific theories to yield underlies the formation and application of the multi-valued logic of approximation discussed in this paper. In this logic, inexactness （measured by truth values） is controlled and minimized by means of uniquely designed deductions. We show how the notion of equality （including substitution of equals） is handled within this logic and we apply it to certain principles and interpretations of quantum theory.
基金Y.T.L.acknowledges the financial support from the National Research Foundation of Korea(NRF)(No.NRF-2021R1C1C1005235)D.K.H.acknowledges the financial support from the Korea Institute of Science and Technology(KIST)Institution Program(No.2E31532).
文摘Two-dimensional van der Waals(2D vdW)material-based heterostructure devices have been widely studied for high-end electronic applications owing to their heterojunction properties.In this study,we demonstrate graphene(Gr)-bridge heterostructure devices consisting of laterally series-connected ambipolar semiconductor/Gr-bridge/n-type molybdenum disulfide as a channel material for field-effect transistors(FET).Unlike conventional FET operation,our Gr-bridge devices exhibit nonclassical transfer characteristics(humped transfer curve),thus possessing a negative differential transconductance.These phenomena are interpreted as the operating behavior in two series-connected FETs,and they result from the gate-tunable contact capacity of the Gr-bridge layer.Multi-value logic inverters and frequency tripler circuits are successfully demonstrated using ambipolar semiconductors with narrow-and wide-bandgap materials as more advanced circuit applications based on non-classical transfer characteristics.Thus,we believe that our innovative and straightforward device structure engineering will be a promising technique for future multi-functional circuit applications of 2D nanoelectronics.
文摘This paper proposes the use of the current signal to express logic values and establishes the theory of grounded current switches suitable for I2L circuits.Based on the advantage that current signals are easy to be added, the design technique of I2L circuits by means of the multi-valued current signal is proposed.It is shown that simpler structure of I2L circuits can be obtained with this technique.
文摘To enhance the expressive power and the declarative ability of a deductive database, various CWA (Closed World Assumption) formalizations including the naive CWA, the generalized CWA and the careful CWA are extended to multi-valued logics. The basic idea is to embed logic formulas into some polynomial ring. The extensions can be applied in a uniform manner to any finitely multi-valued logics. Therefore they are also of computational significance.
文摘In cryptology, it is an important topic to study the best affine approach of functions. The best affine approach of Boolean functions has been discussed in ref. [1] by using the Walsh spectrum, of which the key problem is how to represent the correspondence of Boolean functions by using Walsh spectrum. For the multi-valued logical functions so far, the spectral representation of their correspondence has not been presented yet. This let-
文摘A semantic model based on modal logic is proposed in the paperfor the enterprise viewpoint of ODP system. This model formalized the coop-eration relationship among objects within an ODP system. To handle the se-mantic contradiction occurred in federation
文摘Neurons with complex-valued weights have stronger capability because of their multi-valued threshold logic. Neurons with such features may be suitable for solution of different kinds of problems including associative memory,image recognition and digital logical mapping. In this paper,robustness or tolerance is introduced and newly defined for this kind of neuron ac-cording to both their mathematical model and the perceptron neuron's definition of robustness. Also,the most robust design for basic digital logics of multiple variables is proposed based on these robust neurons. Our proof procedure shows that,in robust design each weight only takes the value of i or -i,while the value of threshold is with respect to the number of variables. The results demonstrate the validity and simplicity of using robust neurons for realizing arbitrary digital logical functions.
文摘A lot of research has been done on multiple-valued logic(MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors(CNTFETs) are considered a viable alternative for silicon transistors(MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.
基金Project supported by the National Natural Science Foundation of China
文摘This paper analyses the binary expression of ternary signals and the binary construction of circuits, and proposes the design of a mixed-valued counter by using both binary flip-flops and ternary flip-flops ("tri-flops"). Here a new design of an 8421 BCD up-counter based on the mixed-valued binary-binary-ternary-coded decimal (B2TCD) code using mixed-valued logic is presented.
