There are many kinds of special relationships between multiple-valued logical func-tions and their variables, and they are difficult to be judged from their expressions. In thispaper, some sufficient and necessary con...There are many kinds of special relationships between multiple-valued logical func-tions and their variables, and they are difficult to be judged from their expressions. In thispaper, some sufficient and necessary conditions of the independence and statistical independenceof multiple-valued logical functions on their variables are given. Some conditions of algebraicindependence of multiple-valued logical functions on some of their variables and the way to de-generate a function to the greatest extent are proposed, and some applications of these resultsare indicated. All the results are studied by using Chrestenson spectral techniques.展开更多
In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic...In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic source-coupled logic （SCL）. Its key components, the comparator and the output generator are both based on differential-pair circuit （DPC）, and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.展开更多
Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measu...Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measure for cipher systems to defend against correlation attacks. In terms of Walsh transform, the correlation immunity of binary-valued logic functions, i.e. Boolean functions, was studied in ref. [2], and a展开更多
A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the pr...A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.展开更多
In completeness theories of multiple-valued logic, the characterization of Sheffer functions is an important issue. The solution can be reduced to determining the minimal coverings of precomplete classes. In this pape...In completeness theories of multiple-valued logic, the characterization of Sheffer functions is an important issue. The solution can be reduced to determining the minimal coverings of precomplete classes. In this paper, someFull Symmetric Function Sets (m=3) are proved to be components of the minimal covering of precomplete classes inP k * . Keywords multiple-valued logic - completeness - Sheffer function - precomplete class NoteThis work is supported by the National Natural Science Foundation of China (Grant Nos.60083001 and 60375021).展开更多
This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability o...This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.展开更多
The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.
The BN operation is known as an efficient basic operation in Galois fields GF （2k）, and various algorithms and implementations using binary logic signals have already been proposed. In or- der to reduce the circuit ...The BN operation is known as an efficient basic operation in Galois fields GF （2k）, and various algorithms and implementations using binary logic signals have already been proposed. In or- der to reduce the circuit complexity and long latency of BN operations, a novel algorithm and its sys- tolic architecture are proposed based on multiple-value logic （MVL）. In the very large scale integra- tion （VLSI） realization, a kind of multiple-valued current-mode （MVCM） circuit structure is presen- ted and in which the combination of dynamic source-coupled logic （SCL） and different-pair circuits （DPCs） is employed to improve the switching speed and reduce the power dissipation. The perform- ance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The transistor numbers and the delay are superior to corresponding binary CMOS implementation. The combination of MVCM cir- cuits and relevant algorithms based on MVL seems to be potential solution for high performance a- rithmetic operationsin Galois fields GF（2k）.展开更多
An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits...An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones.展开更多
文摘There are many kinds of special relationships between multiple-valued logical func-tions and their variables, and they are difficult to be judged from their expressions. In thispaper, some sufficient and necessary conditions of the independence and statistical independenceof multiple-valued logical functions on their variables are given. Some conditions of algebraicindependence of multiple-valued logical functions on some of their variables and the way to de-generate a function to the greatest extent are proposed, and some applications of these resultsare indicated. All the results are studied by using Chrestenson spectral techniques.
基金Supported by Beijing Institute of Technology Science Foundation(3050012211106)
文摘In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic source-coupled logic （SCL）. Its key components, the comparator and the output generator are both based on differential-pair circuit （DPC）, and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.
基金Project supported by the National Natural Science FoundationDoctoral Programme Foundation of Institutions of Higher Education
文摘Correlation-immunity is an important concept in cryptology. In ref. [1] Siegenthaler introduced the mathematical definition of correlation-immunity and used the correlation-immunity order of logic functions as a measure for cipher systems to defend against correlation attacks. In terms of Walsh transform, the correlation immunity of binary-valued logic functions, i.e. Boolean functions, was studied in ref. [2], and a
文摘A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.
文摘In completeness theories of multiple-valued logic, the characterization of Sheffer functions is an important issue. The solution can be reduced to determining the minimal coverings of precomplete classes. In this paper, someFull Symmetric Function Sets (m=3) are proved to be components of the minimal covering of precomplete classes inP k * . Keywords multiple-valued logic - completeness - Sheffer function - precomplete class NoteThis work is supported by the National Natural Science Foundation of China (Grant Nos.60083001 and 60375021).
基金supported by the Grant number 600/1792 from the vice presidency of research and technology of Shahid Beheshti University,G.C
文摘This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
基金The Project Supported by National Natural Science Foundation of China
文摘The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.
基金Supported by Science Foundation of Beijing Institute of Technology(20120542012)
文摘The BN operation is known as an efficient basic operation in Galois fields GF （2k）, and various algorithms and implementations using binary logic signals have already been proposed. In or- der to reduce the circuit complexity and long latency of BN operations, a novel algorithm and its sys- tolic architecture are proposed based on multiple-value logic （MVL）. In the very large scale integra- tion （VLSI） realization, a kind of multiple-valued current-mode （MVCM） circuit structure is presen- ted and in which the combination of dynamic source-coupled logic （SCL） and different-pair circuits （DPCs） is employed to improve the switching speed and reduce the power dissipation. The perform- ance is evaluated by HSPICE simulation with 0.18 μm CMOS technology. The transistor numbers and the delay are superior to corresponding binary CMOS implementation. The combination of MVCM cir- cuits and relevant algorithms based on MVL seems to be potential solution for high performance a- rithmetic operationsin Galois fields GF（2k）.
文摘An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones.
